From: Vidya Sagar <vidyas@nvidia.com>
To: Thierry Reding <treding@nvidia.com>,
Jingoo Han <jingoohan1@gmail.com>,
"lorenzo.pieralisi@arm.com" <lorenzo.pieralisi@arm.com>,
"bhelgaas@google.com" <bhelgaas@google.com>
Cc: "gustavo.pimentel@synopsys.com" <gustavo.pimentel@synopsys.com>,
"amurray@thegoodpenguin.co.uk" <amurray@thegoodpenguin.co.uk>,
"robh@kernel.org" <robh@kernel.org>,
"jonathanh@nvidia.com" <jonathanh@nvidia.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"kthota@nvidia.com" <kthota@nvidia.com>,
"mmaddireddy@nvidia.com" <mmaddireddy@nvidia.com>,
"sagar.tv@gmail.com" <sagar.tv@gmail.com>
Subject: Re: [PATCH 0/3] Add support to handle prefetchable memory
Date: Wed, 4 Nov 2020 13:16:57 +0530 [thread overview]
Message-ID: <53277a71-13e5-3e7e-7c51-aca367b99d31@nvidia.com> (raw)
In-Reply-To: <20201026123012.GA356750@ulmo>
Lorenzo / Bjorn,
Could you please review patches-1 & 2 in this series?
For the third patch, we already went with Rob's patch @
http://patchwork.ozlabs.org/project/linux-pci/patch/20201026154852.221483-1-robh@kernel.org/
Thanks,
Vidya Sagar
On 10/26/2020 6:02 PM, Thierry Reding wrote:
> On Sat, Oct 24, 2020 at 04:03:41AM +0000, Jingoo Han wrote:
>> On 10/23/20, 3:57 PM, Vidya Sagar wrote:
>>>
>>> This patch series adds support for configuring the DesignWare IP's ATU
>>> region for prefetchable memory translations.
>>> It first starts by flagging a warning if the size of non-prefetchable
>>> aperture goes beyond 32-bit as PCIe spec doesn't allow it.
>>> And then adds required support for programming the ATU to handle higher
>>> (i.e. >4GB) sizes and then finally adds support for differentiating
>>> between prefetchable and non-prefetchable regions and configuring one of
>>> the ATU regions for prefetchable memory translations purpose.
>>>
>>> Vidya Sagar (3):
>>> PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
>>> PCI: dwc: Add support to program ATU for >4GB memory aperture sizes
>>> PCI: dwc: Add support to handle prefetchable memory mapping
>>
>> For 2nd & 3rd,
>> Acked-by: Jingoo <jingoohan1@gmail.com>
>> But, I still want someone to ack 1st patch, not me.
>>
>> To Vidya,
>> If possible, can you ask your coworker to give 'Tested-by'? It will be very helpful.
>> Thank you.
>
> On next-20201026 (but also going back quite a while) I'm seeing this
> during boot on Jetson AGX Xavier (Tegra194):
>
> [ 3.493382] ahci 0001:01:00.0: version 3.0
> [ 3.493889] ahci 0001:01:00.0: SSS flag set, parallel bus scan disabled
> [ 4.497706] ahci 0001:01:00.0: controller reset failed (0xffffffff)
> [ 4.498114] ahci: probe of 0001:01:00.0 failed with error -5
>
> After applying this series, AHCI over PCI is back to normal:
>
> [ 3.543230] ahci 0001:01:00.0: AHCI 0001.0000 32 slots 1 ports 6 Gbps 0x1 impl SATA mode
> [ 3.550841] ahci 0001:01:00.0: flags: 64bit ncq sntf led only pmp fbs pio slum part sxs
> [ 3.559747] scsi host0: ahci
> [ 3.561998] ata1: SATA max UDMA/133 abar m512@0x1230010000 port 0x1230010100 irq 63
>
> So for the series:
>
> Tested-by: Thierry Reding <treding@nvidia.com>
>
next prev parent reply other threads:[~2020-11-04 7:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 19:56 Vidya Sagar
2020-10-23 19:56 ` [PATCH 1/3] PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit Vidya Sagar
2020-10-26 17:51 ` Rob Herring
2020-10-23 19:56 ` [PATCH 2/3] PCI: dwc: Add support to program ATU for >4GB memory aperture sizes Vidya Sagar
2020-10-26 17:51 ` Rob Herring
2020-10-23 19:56 ` [PATCH 3/3] PCI: dwc: Add support to handle prefetchable memory mapping Vidya Sagar
2020-10-26 15:40 ` Rob Herring
2020-10-24 4:03 ` [PATCH 0/3] Add support to handle prefetchable memory Jingoo Han
2020-10-26 12:32 ` Thierry Reding
2020-11-04 7:46 ` Vidya Sagar [this message]
2020-11-17 4:38 ` Vidya Sagar
2020-11-17 12:10 ` [PATCH 0/3] Add support to handle prefetchable memoryg Lorenzo Pieralisi
2020-11-17 17:34 ` Vidya Sagar
2020-11-18 10:29 ` [PATCH 0/3] Add support to handle prefetchable memory Lorenzo Pieralisi
2020-11-04 9:50 ` Jon Hunter
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