From: Heinrich Schuchardt <xypron.glpk@gmx.de>
To: Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
devicetree@vger.kernel.org
Subject: [RFC] dt-bindings: riscv: enum for riscv,isa
Date: Tue, 6 Apr 2021 21:05:34 +0200 [thread overview]
Message-ID: <5385012d-9f09-d7d9-7b6a-cef7de2d4056@gmx.de> (raw)
In Documentation/devicetree/bindings/riscv/cpus.yaml I find for riscv,isa:
enum:
- rv64imac
- rv64imafdc
This implies that 'rv64imafc' or 'rv64imafdqc' would be illegal values
while these combinations of extensions would be compliant with "The
RISC-V Instruction Set Manual".
To me it does not make much sense to try to enumerate all permissible
permutations of RISC-V extensions.
Shouldn't this enum be removed and replaced by examples?
Best regards
Heinrich
next reply other threads:[~2021-04-06 19:05 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-06 19:05 Heinrich Schuchardt [this message]
2021-04-23 3:32 ` Palmer Dabbelt
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