Re: [PATCH v4] ASoC: wm8978: add missing BCLK divider setup

[Richard Fitzgerald <rf@opensource.cirrus.com>]

On 08/10/2025 5:04 pm, Brian Sune wrote:
> In previous WM8978 codec driver versions, wm8978_set_dai_clkdiv
> might not have been called for BCLK, leaving the bit clock
> divider unconfigured. This could cause incorrect or unstable audio
> clocks depending on sample rate and word length.
> 
> This patch adds a check in wm8978_hw_params: if the BCLK divider
> has not been set via wm8978_set_dai_clkdiv, it is dynamically
> calculated and configured at runtime.
> This ensures that BCLK is always correctly set, whether the
> machine driver configures it explicitly or not.
> 
> Apart from this core patch, due to request from Mark Brown and
> Charles Keepax. Overclock BCLK setup is applied, and dropped the
> possible lowest error BCLK result.

Selecting a lowest-error rate is not valid I2S.
You must have enough BCLK cycles to send all the data. If number
of BCLK cycles < number of sample bits you cannot send all the
sample bits. So that would be an incorrect setup.

> On top of the overclocking,

Using a higher BCLK is valid I2S. In fact, it is exactly defined in the
I2S specification that there can be more BCLK cycles than data bits
and the RX end should ignore extra cycles.

> warning message is given to user as a reminding.

Warning the user that you selected the correct BCLK is strange.

> This patch author do not agree with this design nor
> concept from first place!

For example if you are sending stereo 16-bit samples at 48 kHz you must
have a BCLK at least 48000 * 16 * 2 = 1536000 Hz.

If the _nearest_ BCLK is < 1536000 you don't have enough clock
cycles to send all the sample bits.