From: Florian Fainelli <f.fainelli@gmail.com>
To: Florian Fainelli <f.fainelli@gmail.com>,
linux-arm-kernel@lists.infradead.org
Cc: "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates
Date: Sun, 6 Sep 2020 12:43:56 -0700 [thread overview]
Message-ID: <54f4b19d-8feb-c780-6b5d-2b6ab6c97d30@gmail.com> (raw)
In-Reply-To: <20200904205055.3309379-1-f.fainelli@gmail.com>
On 9/4/2020 1:50 PM, Florian Fainelli wrote:
> This patch series adds support for two new STB chips: 72164 and 72165
> and allows them to be tuned the same way other Brahma-B53 chips are.
>
> The last two changes are some minor configuration changes to the
> read-ahead cache logic to improve performance for Cortex-A72 based
> systems.
Series applied to drivers/next, there was an incorrectly updated comment
in the last patch that was removed.
--
Florian
next prev parent reply other threads:[~2020-09-06 19:45 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-04 20:50 Florian Fainelli
2020-09-04 20:50 ` [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 Florian Fainelli
2020-09-04 20:50 ` [PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 Florian Fainelli
2020-09-04 20:50 ` [PATCH 2/4] soc: " Florian Fainelli
2020-09-04 20:50 ` [PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 Florian Fainelli
2020-09-04 20:50 ` [PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines Florian Fainelli
2020-09-06 19:43 ` Florian Fainelli [this message]
-- strict thread matches above, loose matches on Subject: below --
2019-12-10 23:30 [PATCH 0/4] soc: bcm: brcmstb: biuctrl updates Florian Fainelli
2020-01-05 21:47 ` Florian Fainelli
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