[PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates

mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed

* [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates
@ 2020-09-04 20:50 Florian Fainelli
  2020-09-04 20:50 ` [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 Florian Fainelli
                   ` (5 more replies)
  0 siblings, 6 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

This patch series adds support for two new STB chips: 72164 and 72165
and allows them to be tuned the same way other Brahma-B53 chips are.

The last two changes are some minor configuration changes to the
read-ahead cache logic to improve performance for Cortex-A72 based
systems.

Florian Fainelli (4):
  soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
  soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
  soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to
    +/- 2
  soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4
    consecutive lines

 drivers/soc/bcm/brcmstb/biuctrl.c | 30 +++++++++++++++++++++++++-----
 1 file changed, 25 insertions(+), 5 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
@ 2020-09-04 20:50 ` Florian Fainelli
  2020-09-04 20:50 ` [PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 Florian Fainelli
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

72164 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index 95602ece51d4..a4b01894a9ad 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -130,6 +130,7 @@ static int __init mcp_write_pairing_set(void)
 static const u32 a72_b53_mach_compat[] = {
 	0x7211,
 	0x7216,
+	0x72164,
 	0x7255,
 	0x7260,
 	0x7268,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
  2020-09-04 20:50 ` [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 Florian Fainelli
@ 2020-09-04 20:50 ` Florian Fainelli
  2020-09-04 20:50 ` [PATCH 2/4] soc: " Florian Fainelli
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index a4b01894a9ad..d448a89ceb27 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -131,6 +131,7 @@ static const u32 a72_b53_mach_compat[] = {
 	0x7211,
 	0x7216,
 	0x72164,
+	0x72165,
 	0x7255,
 	0x7260,
 	0x7268,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 2/4] soc: brcmstb: biuctrl: Tune MCP settings for 72165
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
  2020-09-04 20:50 ` [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 Florian Fainelli
  2020-09-04 20:50 ` [PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 Florian Fainelli
@ 2020-09-04 20:50 ` Florian Fainelli
  2020-09-04 20:50 ` [PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 Florian Fainelli
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

72165 uses a Brahma-B53 CPU and its Bus Interface Unit, tune it
according to the existing values we have.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/biuctrl.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index a4b01894a9ad..d448a89ceb27 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -131,6 +131,7 @@ static const u32 a72_b53_mach_compat[] = {
 	0x7211,
 	0x7216,
 	0x72164,
+	0x72165,
 	0x7255,
 	0x7260,
 	0x7268,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
                   ` (2 preceding siblings ...)
  2020-09-04 20:50 ` [PATCH 2/4] soc: " Florian Fainelli
@ 2020-09-04 20:50 ` Florian Fainelli
  2020-09-04 20:50 ` [PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines Florian Fainelli
  2020-09-06 19:43 ` [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

Change the RAC prefetch distance from +/- 1 to +/- 2 for Cortex-A72 CPUs
since this provides an average of a 3.8% performance increase for
synthetic memcpy benchmarks.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/biuctrl.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index d448a89ceb27..28f69cc0df51 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -20,6 +20,8 @@
 #define RACENDATA_SHIFT			6
 #define RAC_CPU_SHIFT			8
 #define RACCFG_MASK			0xff
+#define DPREF_LINE_2_SHIFT		24
+#define DPREF_LINE_2_MASK		0xff
 
 /* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
 #define RAC_DATA_INST_EN_MASK		(1 << RACPREFINST_SHIFT | \
@@ -50,6 +52,7 @@ enum cpubiuctrl_regs {
 	CPU_MCP_FLOW_REG,
 	CPU_WRITEBACK_CTRL_REG,
 	RAC_CONFIG0_REG,
+	RAC_CONFIG1_REG,
 	NUM_CPU_BIUCTRL_REGS,
 };
 
@@ -58,7 +61,7 @@ static inline u32 cbc_readl(int reg)
 	int offset = cpubiuctrl_regs[reg];
 
 	if (offset == -1 ||
-	    (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg == RAC_CONFIG0_REG))
+	    (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
 		return (u32)-1;
 
 	return readl_relaxed(cpubiuctrl_base + offset);
@@ -69,7 +72,7 @@ static inline void cbc_writel(u32 val, int reg)
 	int offset = cpubiuctrl_regs[reg];
 
 	if (offset == -1 ||
-	    (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg == RAC_CONFIG0_REG))
+	    (IS_ENABLED(CONFIG_CACHE_B15_RAC) && reg >= RAC_CONFIG0_REG))
 		return;
 
 	writel(val, cpubiuctrl_base + offset);
@@ -80,6 +83,7 @@ static const int b15_cpubiuctrl_regs[] = {
 	[CPU_MCP_FLOW_REG] = -1,
 	[CPU_WRITEBACK_CTRL_REG] = -1,
 	[RAC_CONFIG0_REG] = -1,
+	[RAC_CONFIG1_REG] = -1,
 };
 
 /* Odd cases, e.g: 7260A0 */
@@ -88,6 +92,7 @@ static const int b53_cpubiuctrl_no_wb_regs[] = {
 	[CPU_MCP_FLOW_REG] = 0x0b4,
 	[CPU_WRITEBACK_CTRL_REG] = -1,
 	[RAC_CONFIG0_REG] = 0x78,
+	[RAC_CONFIG1_REG] = 0x7c,
 };
 
 static const int b53_cpubiuctrl_regs[] = {
@@ -95,6 +100,7 @@ static const int b53_cpubiuctrl_regs[] = {
 	[CPU_MCP_FLOW_REG] = 0x0b4,
 	[CPU_WRITEBACK_CTRL_REG] = 0x22c,
 	[RAC_CONFIG0_REG] = 0x78,
+	[RAC_CONFIG1_REG] = 0x7c,
 };
 
 static const int a72_cpubiuctrl_regs[] = {
@@ -102,6 +108,7 @@ static const int a72_cpubiuctrl_regs[] = {
 	[CPU_MCP_FLOW_REG] = 0x1c,
 	[CPU_WRITEBACK_CTRL_REG] = 0x20,
 	[RAC_CONFIG0_REG] = 0x08,
+	[RAC_CONFIG1_REG] = 0x0c,
 };
 
 static int __init mcp_write_pairing_set(void)
@@ -167,7 +174,7 @@ static const u32 a72_b53_mach_compat[] = {
 static void __init a72_b53_rac_enable_all(struct device_node *np)
 {
 	unsigned int cpu;
-	u32 enable = 0;
+	u32 enable = 0, pref_dist;
 
 	if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
 		return;
@@ -175,10 +182,15 @@ static void __init a72_b53_rac_enable_all(struct device_node *np)
 	if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
 		return;
 
-	for_each_possible_cpu(cpu)
+	pref_dist = cbc_readl(RAC_CONFIG1_REG);
+	for_each_possible_cpu(cpu) {
 		enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
+		if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
+			pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
+	}
 
 	cbc_writel(enable, RAC_CONFIG0_REG);
+	cbc_writel(pref_dist, RAC_CONFIG1_REG);
 
 	pr_info("%pOF: Broadcom %s read-ahead cache\n",
 		np, cpubiuctrl_regs == a72_cpubiuctrl_regs ?
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
                   ` (3 preceding siblings ...)
  2020-09-04 20:50 ` [PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 Florian Fainelli
@ 2020-09-04 20:50 ` Florian Fainelli
  2020-09-06 19:43 ` [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-04 20:50 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

Change the RACPREFDATA(x) setting to prefetch the next 256-byte line
after 4 consecutive lines have been used, instead of after 2 consecutive
lines. This does improve the synthetic memcpy benchmark by an additional
+0.5% on top of the previous change for Cortex-A72 CPUs.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 drivers/soc/bcm/brcmstb/biuctrl.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/bcm/brcmstb/biuctrl.c b/drivers/soc/bcm/brcmstb/biuctrl.c
index 28f69cc0df51..63864b6dea2e 100644
--- a/drivers/soc/bcm/brcmstb/biuctrl.c
+++ b/drivers/soc/bcm/brcmstb/biuctrl.c
@@ -23,7 +23,9 @@
 #define DPREF_LINE_2_SHIFT		24
 #define DPREF_LINE_2_MASK		0xff
 
-/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
+/* Bitmask to enable instruction and data prefetching with a 256-bytes stride,
+ * prefetch next 256-byte line after 4 consecutive lines used
+ */
 #define RAC_DATA_INST_EN_MASK		(1 << RACPREFINST_SHIFT | \
 					 RACENPREF_MASK << RACENINST_SHIFT | \
 					 1 << RACPREFDATA_SHIFT | \
@@ -174,7 +176,7 @@ static const u32 a72_b53_mach_compat[] = {
 static void __init a72_b53_rac_enable_all(struct device_node *np)
 {
 	unsigned int cpu;
-	u32 enable = 0, pref_dist;
+	u32 enable = 0, pref_dist, shift;
 
 	if (IS_ENABLED(CONFIG_CACHE_B15_RAC))
 		return;
@@ -184,9 +186,13 @@ static void __init a72_b53_rac_enable_all(struct device_node *np)
 
 	pref_dist = cbc_readl(RAC_CONFIG1_REG);
 	for_each_possible_cpu(cpu) {
+		shift = cpu * RAC_CPU_SHIFT + RACPREFDATA_SHIFT;
 		enable |= RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT);
-		if (cpubiuctrl_regs == a72_cpubiuctrl_regs)
+		if (cpubiuctrl_regs == a72_cpubiuctrl_regs) {
+			enable &= ~(RACENPREF_MASK << shift);
+			enable |= 3 << shift;
 			pref_dist |= 1 << (cpu + DPREF_LINE_2_SHIFT);
+		}
 	}
 
 	cbc_writel(enable, RAC_CONFIG0_REG);
-- 
2.25.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates
  2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
                   ` (4 preceding siblings ...)
  2020-09-04 20:50 ` [PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines Florian Fainelli
@ 2020-09-06 19:43 ` Florian Fainelli
  5 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-09-06 19:43 UTC (permalink / raw)
  To: Florian Fainelli, linux-arm-kernel
  Cc: maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, open list



On 9/4/2020 1:50 PM, Florian Fainelli wrote:
> This patch series adds support for two new STB chips: 72164 and 72165
> and allows them to be tuned the same way other Brahma-B53 chips are.
> 
> The last two changes are some minor configuration changes to the
> read-ahead cache logic to improve performance for Cortex-A72 based
> systems.

Series applied to drivers/next, there was an incorrectly updated comment 
in the last patch that was removed.
-- 
Florian

^ permalink raw reply	[flat|nested] 9+ messages in thread

* [PATCH 0/4] soc: bcm: brcmstb: biuctrl updates
@ 2019-12-10 23:30 Florian Fainelli
  2020-01-05 21:47 ` Florian Fainelli
  0 siblings, 1 reply; 9+ messages in thread
From: Florian Fainelli @ 2019-12-10 23:30 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Florian Fainelli, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE,
	open list

Hi all,

This patch series updates the Broadcom STB BIUCTRL register code to
support the latest and greatest chips (7255, 7216, 7211) and also fixes
the 7260A0 and B0 chips to use the correct tuning parameters.

Florian Fainelli (4):
  soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interface
  soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216
  soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211
  soc: bcm: brcmstb: biuctrl: Update programming for 7211

 drivers/soc/bcm/brcmstb/biuctrl.c | 30 ++++++++++++++++++++++--------
 1 file changed, 22 insertions(+), 8 deletions(-)

-- 
2.17.1


^ permalink raw reply	[flat|nested] 9+ messages in thread

* Re: [PATCH 0/4] soc: bcm: brcmstb: biuctrl updates
  2019-12-10 23:30 [PATCH 0/4] soc: bcm: brcmstb: biuctrl updates Florian Fainelli
@ 2020-01-05 21:47 ` Florian Fainelli
  0 siblings, 0 replies; 9+ messages in thread
From: Florian Fainelli @ 2020-01-05 21:47 UTC (permalink / raw)
  To: Florian Fainelli, linux-arm-kernel
  Cc: maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, open list



On 12/10/2019 3:30 PM, Florian Fainelli wrote:
> Hi all,
> 
> This patch series updates the Broadcom STB BIUCTRL register code to
> support the latest and greatest chips (7255, 7216, 7211) and also fixes
> the 7260A0 and B0 chips to use the correct tuning parameters.
> 
> Florian Fainelli (4):
>   soc: bcm: brcmstb: biuctrl: Tune 7260 BIU interface
>   soc: bcm: brcmstb: biuctrl: Tune interface for 7255 and 7216
>   soc: bcm: brcmstb: biuctrl: Update layout for A72 on 7211
>   soc: bcm: brcmstb: biuctrl: Update programming for 7211

Series applied to drivers/next.
-- 
Florian

^ permalink raw reply	[flat|nested] 9+ messages in thread

end of thread, other threads:[~2020-09-06 19:45 UTC | newest]

Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-09-04 20:50 [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
2020-09-04 20:50 ` [PATCH 1/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72164 Florian Fainelli
2020-09-04 20:50 ` [PATCH 2/4] soc: bcm: brcmstb: biuctrl: Tune MCP settings for 72165 Florian Fainelli
2020-09-04 20:50 ` [PATCH 2/4] soc: " Florian Fainelli
2020-09-04 20:50 ` [PATCH 3/4] soc: bcm: brcmstb: biuctrl: Change RAC prefetch distance from +/-1 to +/- 2 Florian Fainelli
2020-09-04 20:50 ` [PATCH 4/4] soc: bcm: brcmstb: biuctrl: Change RAC data line prefetching after 4 consecutive lines Florian Fainelli
2020-09-06 19:43 ` [PATCH 0/4] soc: bcm: brcmstb: BIUCTRL updates Florian Fainelli
  -- strict thread matches above, loose matches on Subject: below --
2019-12-10 23:30 [PATCH 0/4] soc: bcm: brcmstb: biuctrl updates Florian Fainelli
2020-01-05 21:47 ` Florian Fainelli

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®