Re: [PATCH 1/2] dt-bindings: clock: Add DISPCC and reset controller for GLYMUR SoC

[Taniya Das <taniya.das@oss.qualcomm.com>]

On 8/29/2025 1:42 PM, Dmitry Baryshkov wrote:
> On Fri, Aug 29, 2025 at 01:28:03PM +0530, Taniya Das wrote:
>> Add the device tree bindings for the display clock controller which are
>> required on Qualcomm Glymur SoC.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> ---
>>  .../bindings/clock/qcom,glymur-dispcc.yaml         |  99 ++++++++++++++++++
>>  include/dt-bindings/clock/qcom,glymur-dispcc.h     | 114 +++++++++++++++++++++
>>  2 files changed, 213 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..063da2416dbaed764b8579a090bc5fc0531ab60d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/qcom,glymur-dispcc.yaml
>> @@ -0,0 +1,99 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Display Clock & Reset Controller on GLYMUR
>> +
>> +maintainers:
>> +  - Taniya Das <taniya.das@oss.qualcomm.com>
>> +
>> +description: |
>> +  Qualcomm display clock control module which supports the clocks, resets and
>> +  power domains for the MDSS instances on GLYMUR SoC.
>> +
>> +  See also:
>> +    include/dt-bindings/clock/qcom,dispcc-glymur.h
>> +
>> +properties:
>> +  compatible:
>> +    enum:
>> +      - qcom,glymur-dispcc
>> +
>> +  clocks:
>> +    items:
>> +      - description: Board CXO clock
>> +      - description: Board sleep clock
>> +      - description: DisplayPort 0 link clock
>> +      - description: DisplayPort 0 VCO div clock
>> +      - description: DisplayPort 1 link clock
>> +      - description: DisplayPort 1 VCO div clock
>> +      - description: DisplayPort 2 link clock
>> +      - description: DisplayPort 2 VCO div clock
>> +      - description: DisplayPort 3 link clock
>> +      - description: DisplayPort 3 VCO div clock
>> +      - description: DSI 0 PLL byte clock
>> +      - description: DSI 0 PLL DSI clock
>> +      - description: DSI 1 PLL byte clock
>> +      - description: DSI 1 PLL DSI clock
>> +      - description: Standalone PHY 0 PLL link clock
>> +      - description: Standalone PHY 0 VCO div clock
>> +      - description: Standalone PHY 1 PLL link clock
>> +      - description: Standalone PHY 1 VCO div clock
>> +
>> +  power-domains:
>> +    description:
>> +      A phandle and PM domain specifier for the MMCX power domain.
>> +    maxItems: 1
>> +
>> +  required-opps:
>> +    description:
>> +      A phandle to an OPP node describing required MMCX performance point.
>> +    maxItems: 1
>> +
>> +required:
>> +  - compatible
>> +  - clocks
>> +  - power-domains
>> +  - '#power-domain-cells'
>> +
>> +allOf:
>> +  - $ref: qcom,gcc.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,glymur-dispcc.h>
> Should not be needed

Sure Dmitry, will remove this in the next patchset.

-- 
Thanks,
Taniya Das