Re: [PATCH] clk: qcom: rpmh: Fix LNBBCLK3 divider for X1E80100

[Taniya Das <taniya.das@oss.qualcomm.com>]

On 2/11/2026 11:52 PM, Taniya Das wrote:
> DEFINE_CLK_RPMH_VRM(clk5, _a1, "clka5", 1);
> +DEFINE_CLK_RPMH_VRM(clk8, _a1, "clka8", 1);
>  
>  DEFINE_CLK_RPMH_VRM(clk3, _a2, "clka3", 2);
>  DEFINE_CLK_RPMH_VRM(clk4, _a2, "clka4", 2);
> @@ -840,8 +841,8 @@ static struct clk_hw *x1e80100_rpmh_clocks[] = {
>  	[RPMH_LN_BB_CLK1_A]	= &clk_rpmh_clk6_a2_ao.hw,
>  	[RPMH_LN_BB_CLK2]	= &clk_rpmh_clk7_a2.hw,
>  	[RPMH_LN_BB_CLK2_A]	= &clk_rpmh_clk7_a2_ao.hw,
> -	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a2.hw,
> -	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a2_ao.hw,
> +	[RPMH_LN_BB_CLK3]	= &clk_rpmh_clk8_a1.hw,
> +	[RPMH_LN_BB_CLK3_A]	= &clk_rpmh_clk8_a1_ao.hw,
>  	[RPMH_RF_CLK3]		= &clk_rpmh_clk3_a2.hw,
>  	[RPMH_RF_CLK3_A]	= &clk_rpmh_clk3_a2_ao.hw,
>  	[RPMH_RF_CLK4]		= &clk_rpmh_clk4_a2.hw,

Bjorn, request is to drop picking this change. This fix was identified
as part of downstream validations, but what I realised late was the DTSI
of hamoa upstream and downstream had a difference in the way the
xo_board frequency was defined. Upstream DTSI xo_board freq = 76.8MHz
and downstream DTSI xo_board = 38.4MHz.

The xo_board frequency seems incorrect(upstream) when I mapped it to HW
design and needs a much more involved change in hamoa DTSI as well as
the RPMH clocks.

I will send out a v2 patch later which should take care to fix.

-- 
Thanks,
Taniya Das