From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Taniya Das <taniya.das@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Sibi Sankar <sibi.sankar@oss.qualcomm.com>,
Rajendra Nayak <quic_rjendra@quicinc.com>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Subject: Re: [PATCH] clk: qcom: rpmh: Fix LNBBCLK3 divider for X1E80100
Date: Thu, 12 Feb 2026 11:38:58 +0100 [thread overview]
Message-ID: <6bf4b94e-6ec6-465d-b0d8-0506860afa6a@oss.qualcomm.com> (raw)
In-Reply-To: <20260211-hamoa_ufs_clk8-v1-1-b537f54e9353@oss.qualcomm.com>
On 2/11/26 7:22 PM, Taniya Das wrote:
> The LNBBCLK3 clock used by the UFS controller runs at 38.4 MHz.
> Update the divider value to generate the correct output frequency.
Does this also apply to e.g. 8550 which seems to have a similar setup?
Konrad
next prev parent reply other threads:[~2026-02-12 10:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-11 18:22 Taniya Das
2026-02-11 19:35 ` Dmitry Baryshkov
2026-02-12 10:38 ` Konrad Dybcio [this message]
2026-02-12 10:39 ` Konrad Dybcio
2026-02-18 17:16 ` Taniya Das
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