From: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
To: Vikash Garodia <vikash.garodia@oss.qualcomm.com>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Bryan O'Donoghue <bod@kernel.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Vishnu Reddy <busanna.reddy@oss.qualcomm.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Subject: Re: [PATCH v4 4/6] media: iris: Move vpu register defines to common header file
Date: Fri, 16 Jan 2026 15:15:54 +0530 [thread overview]
Message-ID: <564c05b4-a41d-df0a-abb8-564b22b9a45e@oss.qualcomm.com> (raw)
In-Reply-To: <20251210-knp_video-v4-4-8d11d840358a@oss.qualcomm.com>
On 12/10/2025 6:06 PM, Vikash Garodia wrote:
> Some of vpu4 register defines are common with vpu3x. Move those into the
> common register defines header. This is done to reuse the defines for
> vpu4 in subsequent patch which enables the power sequence for vpu4.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Co-developed-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
> Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
> Signed-off-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
> ---
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 42 ---------------
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 43 ---------------
> .../platform/qcom/iris/iris_vpu_register_defines.h | 61 ++++++++++++++++++++++
> 3 files changed, 61 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> index 339776a0b4672e246848c3a6a260eb83c7da6a60..cd53bcda3b3e1d6f234486df49a51150a7ec9799 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c
> @@ -11,48 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -#define AON_MVP_NOC_RESET 0x0001F000
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> -#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> -#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> -#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> -#define CORE_CLK_RUN 0x0
> -/* VPU v3.5 */
> -#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
> -
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> -#define CORE_BRIDGE_SW_RESET BIT(0)
> -#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> -#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
> -
> -#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
> -
> -#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> #define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18)
> #define SW_RESET BIT(0)
> #define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20)
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> index fef192a2de48fa47af421632829184c5896326cd..50242fc6b4653a7d74ff64500f40eb8a859a6548 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c
> @@ -11,13 +11,6 @@
> #include "iris_vpu_common.h"
> #include "iris_vpu_register_defines.h"
>
> -#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> -#define AON_BASE_OFFS 0x000E0000
> -
> -#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
> -
> -#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> -#define CLEAR_XTENSA2HOST_INTR BIT(0)
>
> #define CTRL_INIT (CPU_CS_BASE_OFFS + 0x48)
> #define CTRL_STATUS (CPU_CS_BASE_OFFS + 0x4C)
> @@ -35,42 +28,6 @@
> #define UC_REGION_ADDR (CPU_CS_BASE_OFFS + 0x64)
> #define UC_REGION_SIZE (CPU_CS_BASE_OFFS + 0x68)
>
> -#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> -#define HOST2XTENSA_INTR_ENABLE BIT(0)
> -
> -#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> -#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> -#define MSK_CORE_POWER_ON BIT(1)
> -
> -#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> -#define CPU_IC_SOFTINT_H2A_SHFT 0x0
> -
> -#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
> -#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> -#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
> -
> -#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
> -#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> -#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
> -
> -#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> -#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> -#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> -
> -#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> -#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> -#define CTL_AXI_CLK_HALT BIT(0)
> -#define CTL_CLK_HALT BIT(1)
> -
> -#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> -#define RESET_HIGH BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> -#define REQ_POWER_DOWN_PREP BIT(0)
> -
> -#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
> -
> static void iris_vpu_interrupt_init(struct iris_core *core)
> {
> u32 mask_val;
> diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> index fe8a39e5e5a3fc68dc3a706ffdba07a5558163cf..72168b9ffa7385d53d7190265d1c0922ee04a656 100644
> --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h
> @@ -7,11 +7,72 @@
> #define __IRIS_VPU_REGISTER_DEFINES_H__
>
> #define VCODEC_BASE_OFFS 0x00000000
> +#define AON_MVP_NOC_RESET 0x0001F000
> #define CPU_BASE_OFFS 0x000A0000
> #define WRAPPER_BASE_OFFS 0x000B0000
> +#define WRAPPER_TZ_BASE_OFFS 0x000C0000
> +#define AON_BASE_OFFS 0x000E0000
> +
> +#define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70)
> +
> +#define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000)
> +#define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1))
> +
> +#define AON_WRAPPER_MVP_NOC_RESET_ACK (AON_MVP_NOC_RESET + 0x004)
>
> #define CPU_CS_BASE_OFFS (CPU_BASE_OFFS)
> +#define CPU_IC_BASE_OFFS (CPU_BASE_OFFS)
> +
> +#define CPU_CS_A2HSOFTINTCLR (CPU_CS_BASE_OFFS + 0x1C)
> +#define CLEAR_XTENSA2HOST_INTR BIT(0)
> +
> +#define CPU_CS_H2XSOFTINTEN (CPU_CS_BASE_OFFS + 0x148)
> +#define HOST2XTENSA_INTR_ENABLE BIT(0)
> +
> +#define CPU_IC_SOFTINT (CPU_IC_BASE_OFFS + 0x150)
> +#define CPU_IC_SOFTINT_H2A_SHFT 0x0
> +
> +#define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160)
> +#define CORE_BRIDGE_SW_RESET BIT(0)
> +#define CORE_BRIDGE_HW_RESET_DISABLE BIT(1)
> +
> +#define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168)
> +#define MSK_SIGNAL_FROM_TENSILICA BIT(0)
> +#define MSK_CORE_POWER_ON BIT(1)
>
> +#define WRAPPER_INTR_STATUS (WRAPPER_BASE_OFFS + 0x0C)
> +#define WRAPPER_INTR_STATUS_A2HWD_BMSK BIT(3)
> +#define WRAPPER_INTR_STATUS_A2H_BMSK BIT(2)
> +
> +#define WRAPPER_INTR_MASK (WRAPPER_BASE_OFFS + 0x10)
> +#define WRAPPER_INTR_MASK_A2HWD_BMSK BIT(3)
> +#define WRAPPER_INTR_MASK_A2HCPU_BMSK BIT(2)
> +
> +#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x54)
> +#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58)
> +#define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C)
> +#define REQ_POWER_DOWN_PREP BIT(0)
> +
> +#define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60)
> +#define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */
> +#define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */
> +#define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */
> +
> +#define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78)
> #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80)
> +#define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88)
> +#define CORE_CLK_RUN 0x0
> +
> +#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
> +
> +#define WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS + 0x14)
> +#define CTL_AXI_CLK_HALT BIT(0)
> +#define CTL_CLK_HALT BIT(1)
> +
> +#define WRAPPER_TZ_QNS4PDXFIFO_RESET (WRAPPER_TZ_BASE_OFFS + 0x18)
> +#define RESET_HIGH BIT(0)
> +
> +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
> +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
>
> #endif
>
Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com>
Thanks,
Dikshita
next prev parent reply other threads:[~2026-01-16 9:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-10 12:35 [PATCH v4 0/6] media: iris: prepare support for video codecs on Qcom vpu4 platform Vikash Garodia
2025-12-10 12:35 ` [PATCH v4 1/6] media: iris: Add support for multiple clock sources Vikash Garodia
2026-01-16 9:38 ` Dikshita Agarwal
2025-12-10 12:36 ` [PATCH v4 2/6] media: iris: Add support for multiple TZ content protection(CP) configs Vikash Garodia
2026-01-16 9:39 ` Dikshita Agarwal
2025-12-10 12:36 ` [PATCH v4 3/6] media: iris: Introduce buffer size calculations for vpu4 Vikash Garodia
2026-01-16 10:31 ` Dikshita Agarwal
2025-12-10 12:36 ` [PATCH v4 4/6] media: iris: Move vpu register defines to common header file Vikash Garodia
2025-12-10 15:03 ` Dmitry Baryshkov
2025-12-10 15:47 ` Vikash Garodia
2025-12-10 21:26 ` Bryan O'Donoghue
2025-12-10 23:35 ` Dmitry Baryshkov
2026-01-16 9:45 ` Dikshita Agarwal [this message]
2025-12-10 12:36 ` [PATCH v4 5/6] media: iris: Move vpu35 specific api to common to use for vpu4 Vikash Garodia
2026-01-16 9:47 ` Dikshita Agarwal
2025-12-10 12:36 ` [PATCH v4 6/6] media: iris: Introduce vpu ops for vpu4 with necessary hooks Vikash Garodia
2026-01-16 9:51 ` Dikshita Agarwal
2026-01-16 10:46 ` Krzysztof Kozlowski
2026-01-16 11:27 ` Vikash Garodia
2026-01-16 11:54 ` Krzysztof Kozlowski
2026-01-16 12:58 ` Bryan O'Donoghue
2026-01-16 11:30 ` Dikshita Agarwal
2026-01-16 11:53 ` Krzysztof Kozlowski
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