Re: [RESEND PATCH v7] mtd: spi-nor: add hisilicon spi-nor flash controller driver

[Jiancheng Xue <xuejiancheng@huawei.com>]

Hi Brian，
   Thank you very much for your comments.

On 2016/3/8 6:52, Brian Norris wrote:
[...]
>>
>> diff --git a/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt
>> new file mode 100644
>> index 0000000..7407147
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/spi/spi-hisi-sfc.txt
> 
> This is not a SPI controller (or is it? it looks like a SPI NOR
> controller that doesn't do generic SPI), so it shouldn't go in the spi/
> directory.
> 
OK. I'll move this file into Documentation/devicetree/bindings/mtd.

>> @@ -0,0 +1,25 @@
>> +HiSilicon SPI-NOR Flash Controller
>> +
>> +Required properties:
>> +- compatible : Should be "hisilicon,hisi-sfc" and one of the following strings:
>> +		"hisilicon,hi3519-sfc"
>> +- address-cells : number of cells required to define a chip select
>> +        address on the SPI bus. Should be set to 1. See spi-bus.txt.
> 
> This is not exactly a typical SPI bus, though I suppose some of that
> documentation could apply...
> 

OK. I'll modify the description.

[...]
>> +static int hisi_spi_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
>> +		int len)
>> +{
>> +	struct hifmc_priv *priv = nor->priv;
>> +	struct hifmc_host *host = priv->host;
>> +	int ret;
>> +
>> +	ret = hisi_spi_nor_send_cmd(nor, opcode, len);
>> +	if (ret)
>> +		return ret;
>> +
>> +	memcpy(buf, host->iobase, len);
> 
> sparse doesn't like any of these memcpy()'s, since that's __iomem. Are
> you sure you want a regular memcpy here, and elsewhere?
> 
It's not a must to use memcpy though host->iobase represents a segment of inner memory
which stores data from flash device byte by byte.  I will give up using memcpy here and
hisi_spi_nor_write_reg() in next version. Thank you!

>> +
>> +	return 0;
>> +}
>> +
[...]
>> +static void hisi_spi_nor_dma_transfer(struct spi_nor *nor, u32 start_off,
>> +		u32 dma_buf, u32 len, u8 op_type)
> 
> Does this controller support 64-bit addresses? What if you see LPAE, or
> an ARM64 CPU? It'd be nice if you don't truncate potentially 64-bit
> dma_buf down to u32.
> 
> Brian
> 
No, this controller just supports 32-bit addresses. So I think I have to truncate 64-bit dma_buf. :(

Thank you very much!

Regards,
Jiancheng