Re: [PATCH 1/3] dt-bindings: pinctrl: s32g2-siul2: describe EIRQ input mux registers

[Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>]

On 10/8/2026 10:20 AM, Conor Dooley wrote:
> On Thu, Oct 08, 2026 at 09:14:34AM +0200, Khristine Andreea Barbulescu wrote:
>> The SIUL2 external interrupt lines (EIRQ0-EIRQ31) on S32G2/S32G3 are not
>> hard-wired to fixed pads. Each EIRQ line has its own input multiplexer,
>> implemented by the IMCR398-IMCR429 registers, whose Source Signal Select
>> (SSS) field selects which pad signal feeds the edge detector.
>>
>> These registers were previously listed as reserved and were absent from
>> the reg list. Add a dedicated entry for the IMCR398-IMCR429 EIRQ input
>> multiplexer window between the two regular IMCR groups, update the
>> example and the minimum item count for the GPIO/EIRQ variant, and drop
>> IMCR398-IMCR429 from the reserved-index note.
>>
>> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu@oss.nxp.com>
>> ---
>>  .../bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml        | 9 +++++++--
>>  1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> index 36f2393fa406..ecf6d61a80e9 100644
>> --- a/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> +++ b/Documentation/devicetree/bindings/pinctrl/nxp,s32g2-siul2-pinctrl.yaml
>> @@ -23,7 +23,9 @@ description: |
>>    are used for external interrupt configuration.
>>  
>>    Please note that some register indexes are reserved in S32G2, such as
>> -  MSCR102-MSCR111, MSCR123-MSCR143, IMCR84-IMCR118 and IMCR398-IMCR429.
>> +  MSCR102-MSCR111, MSCR123-MSCR143 and IMCR84-IMCR118. IMCR398-IMCR429
>> +  are not regular pin IMCRs but the EIRQ input multiplexer registers,
>> +  which select the pad signal routed to each external interrupt line.
>>  
>>  properties:
>>    compatible:
>> @@ -53,6 +55,7 @@ properties:
>>        - description: MSCR registers group 2 in SIUL2_1
>>        - description: IMCR registers group 0 in SIUL2_0
>>        - description: IMCR registers group 1 in SIUL2_1
>> +      - description: IMCR398-IMCR429 EIRQ input multiplexer registers in SIUL2_1
> 
> Isn't mid-list insertion here a compatibility break, since there's no
> reg-names property here? Seems like this can just be added at the end,
> without an impact on existing users?
>

Hi Conor,

You're right. I placed it mid-list because the EIRQ window (IMCR398-IMCR429)
physically sits between the two IMCR groups in the SIUL2_1 address map.
But I'll move it to the end of the reg list in v2.
>>        - description: IMCR registers group 2 in SIUL2_1
>>        - description: PGPDO registers in SIUL2_0
>>        - description: PGPDI registers in SIUL2_0
>> @@ -141,7 +144,7 @@ oneOf:
>>        - interrupts
>>      properties:
>>        reg:
>> -        minItems: 11
>> +        minItems: 12
> 
> Why is the new reg mandatory? I didn't catch the explanation for that.
> 
> Thanks,
> Conor.
>

The current driver just ioremaps the EIRQ region unconditionally, which is
what forced the bump, but that isn't a real requirement. The EIRQ
window only matters when EIRQ is used.
In v2 I'll keep minItems at 11 and make the window optional: when it's absent
the driver skips the EIRQ IRQ domain (already tracked via eirq_present) and
EIRQ stays purely additive. Does this approach work for you?

>>  
>>  additionalProperties: false
>>  
>> @@ -162,6 +165,8 @@ examples:
>>                <0x4009ca40 0x150>,
>>                /* IMCR119-IMCR397 registers on siul2_1 */
>>                <0x44010c1c 0x45c>,
>> +              /* IMCR398-IMCR429 (EIRQ input mux) on siul2_1 */
>> +              <0x44011078 0x80>,
>>                /* IMCR430-IMCR495 registers on siul2_1 */
>>                <0x440110f8 0x108>,
>>                /* PGPDO registers on siul2_0 */
>> -- 
>> 2.34.1
>>

On timing: I'll hold the v2 respin a bit longer. As noted in the cover letter,
the series still depends on two changes that haven't landed — the rebase of
94cb9e8f2707 ("pinctrl: s32cc: implement GPIO functionality") onto the GPIO tree
(currently reverted by 04b3818c3bbc) and the reg_mask_xlate alignment with
6c53312b7e2d. Until those settle the series won't apply cleanly.

Regards,
Khristine