Re: [PATCH v8 8/9] phy: qualcomm: qmp-combo: Update QMP PHY with Glymur settings

[Wesley Cheng <wesley.cheng@oss.qualcomm.com>]

On 12/9/2025 3:19 PM, Dmitry Baryshkov wrote:
> On Tue, Dec 09, 2025 at 03:09:44PM -0800, Wesley Cheng wrote:
>> For SuperSpeed USB to work properly, there is a set of HW settings that
>> need to be programmed into the USB blocks within the QMP PHY.  Ensure that
>> these settings follow the latest settings mentioned in the HW programming
>> guide.  The QMP USB PHY on Glymur is a USB43 based PHY that will have some
>> new ways to define certain registers, such as the replacement of TXA/RXA
>> and TXB/RXB register sets.  This was replaced with the LALB register set.
>>
>> There are also some PHY init updates to modify the PCS MISC register space.
>> Without these, the QMP PHY PLL locking fails.
>>
>> Signed-off-by: Wesley Cheng <wesley.cheng@oss.qualcomm.com>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-combo.c          | 285 +++++++++
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-aon-v8.h     |  17 +
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcs-misc-v8.h    |  12 +
>>   .../phy/qualcomm/phy-qcom-qmp-qserdes-lalb-v8.h    | 639 +++++++++++++++++++++
>>   drivers/phy/qualcomm/phy-qcom-qmp-usb43-pcs-v8.h   |  33 ++
>>   .../qualcomm/phy-qcom-qmp-usb43-qserdes-com-v8.h   | 224 ++++++++
>>   drivers/phy/qualcomm/phy-qcom-qmp.h                |   2 +
>>   7 files changed, 1212 insertions(+)
>>
> 
> Does this work without DP tables?
> 

Hi Dmitry,

Yes, it works without DP settings.  I verified it on v7 before sending it 
upstream, which did not include the DP tables.  On this series, I verified 
that the QMP DP block is initialized properly on top of the existing 
support for USB3.

Thanks
Wesley Cheng