mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
	Mathieu Poirier <mathieu.poirier@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, coresight@lists.linaro.org,
	mike.leach@linaro.org, leo.yan@linaro.org,
	anshuman.khandual@arm.com, Will Deacon <will.deacon@arm.com>
Subject: Re: [PATCH v5 05/19] arm64: Add support for trace synchronization barrier
Date: Wed, 24 Mar 2021 17:06:58 +0000	[thread overview]
Message-ID: <59aec851-e980-0a6d-8ba5-56a35fa5a7a9@arm.com> (raw)
In-Reply-To: <87tup0ikf0.wl-maz@kernel.org>

On 24/03/2021 16:30, Marc Zyngier wrote:
> On Wed, 24 Mar 2021 16:25:12 +0000,
> Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>
>> On 24/03/2021 16:16, Marc Zyngier wrote:
>>> On Wed, 24 Mar 2021 15:51:14 +0000,
>>> Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>>>
>>>> On 24/03/2021 13:49, Marc Zyngier wrote:
>>>>> On Wed, 24 Mar 2021 09:39:13 +0000,
>>>>> Suzuki K Poulose <suzuki.poulose@arm.com> wrote:
>>>>>>
>>>>>> On 23/03/2021 18:21, Catalin Marinas wrote:
>>>>>>> Hi Suzuki?
>>>>>>>
>>>>>>> On Tue, Mar 23, 2021 at 12:06:33PM +0000, Suzuki K Poulose wrote:
>>>>>>>> tsb csync synchronizes the trace operation of instructions.
>>>>>>>> The instruction is a nop when FEAT_TRF is not implemented.
>>>>>>>>
>>>>>>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>>>>>> Cc: Mike Leach <mike.leach@linaro.org>
>>>>>>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>>>>>>> Cc: Will Deacon <will.deacon@arm.com>
>>>>>>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>>>>>>
>>>>>>> How do you plan to merge these patches? If they go via the coresight
>>>>>>> tree:
>>>>>>>
>>>>>>
>>>>>> Ideally all of this should go via the CoreSight tree to have the
>>>>>> dependencies solved at one place. But there are some issues :
>>>>>>
>>>>>> If this makes to 5.13 queue for CoreSight,
>>>>>>
>>>>>> 1) CoreSight next is based on rc2 at the moment and we have fixes gone
>>>>>> into rc3 and later, which this series will depend on. (We could move
>>>>>> the next tree forward to a later rc to solve this).
>>>>>>
>>>>>> 2) There could be conflicts with the kvmarm tree for the KVM host
>>>>>> changes (That has dependency on the TRBE definitions patch).
>>>>>>
>>>>>> If it doesn't make to 5.13 queue, it would be good to have this patch,
>>>>>> the TRBE defintions and the KVM host patches queued for 5.13 (not sure
>>>>>> if this is acceptable) and we could rebase the CoreSight changes on 5.13
>>>>>> and push it to next release.
>>>>>>
>>>>>> I am open for other suggestions.
>>>>>>
>>>>>> Marc, Mathieu,
>>>>>>
>>>>>> Thoughts ?
>>>>>
>>>>> I was planning to take the first two patches in 5.12 as fixes (they
>>>>> are queued already, and would hopefully land in -rc5). If that doesn't
>>>>> fit with the plan, please let me know ASAP.
>>>>
>>>> Marc,
>>>>
>>>> I think it would be better to hold on pushing those patches until we
>>>> have a clarity on how things will go.
>>>
>>> OK. I thought there was a need for these patches to prevent guest
>>> access to the v8.4 self hosted tracing feature that went in 5.12
>>> though[1]... Did I get it wrong?
>>
>> Yes, that is correct. The guest could access the Trace Filter Control
>> register and fiddle with the host settings, without this patch.
>> e.g, it could disable tracing at EL0/EL1, without the host being
>> aware on nVHE host.
> 
> OK, so we definitely do need these patches, don't we? Both? Just one?
> Please have a look at kvmarm/fixes and tell me what I must keep.

Both of them are fixes.

commit "KVM: arm64: Disable guest access to trace filter controls"
  - This fixes guest fiddling with the trace filter control as described 
above.

commit "KVM: arm64: Hide system instruction access to Trace registers"
  - Fixes the Hypervisor to advertise what it doesn't support. i.e
    stop advertising trace system instruction access to a guest.
    Otherwise a guest which trusts the ID registers
    (ID_AA64DFR0_EL1.TRACEVER == 1) can crash while trying to access the
    trace register as we trap the accesses (CPTR_EL2.TTA == 1). On Linux,
    the ETM drivers need a DT explicitly advertising the support. So,
    this is not immediately impacted. And this fix goes a long way back
    in the history, when the CPTR_EL2.TTA was added.

Now, the reason for asking you to hold on is the way this could create
conflicts in merging the rest of the series.

Suzuki

  reply	other threads:[~2021-03-24 17:10 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-23 12:06 [PATCH v5 00/19] coresight: Add support for ETE and TRBE Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 01/19] [Queued] kvm: arm64: Hide system instruction access to Trace registers Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 02/19] [Queued] kvm: arm64: Disable guest access to trace filter controls Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 03/19] perf: aux: Add flags for the buffer format Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 04/19] perf: aux: Add CoreSight PMU buffer formats Suzuki K Poulose
2021-03-29 16:56   ` Mathieu Poirier
2021-04-19  7:46     ` Peter Zijlstra
2021-03-23 12:06 ` [PATCH v5 05/19] arm64: Add support for trace synchronization barrier Suzuki K Poulose
2021-03-23 18:21   ` Catalin Marinas
2021-03-24  9:39     ` Suzuki K Poulose
2021-03-24 13:49       ` Marc Zyngier
2021-03-24 15:51         ` Suzuki K Poulose
2021-03-24 16:16           ` Marc Zyngier
2021-03-24 16:25             ` Suzuki K Poulose
2021-03-24 16:30               ` Marc Zyngier
2021-03-24 17:06                 ` Suzuki K Poulose [this message]
2021-03-24 17:19                   ` Catalin Marinas
2021-03-24 17:40                     ` Marc Zyngier
2021-03-26 16:31                       ` Mathieu Poirier
2021-03-23 12:06 ` [PATCH v5 06/19] arm64: Add TRBE definitions Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 07/19] arm64: kvm: Enable access to TRBE support for host Suzuki K Poulose
2021-03-26 16:55   ` Mathieu Poirier
2021-03-30 10:16     ` Marc Zyngier
2021-03-30 10:38     ` Suzuki K Poulose
2021-03-30 15:23       ` Mathieu Poirier
2021-03-30 15:34         ` Marc Zyngier
2021-03-30 15:35         ` Greg KH
2021-03-30 16:33           ` Mathieu Poirier
2021-03-30 16:47             ` Greg KH
2021-03-30 16:51               ` Mathieu Poirier
2021-03-30 10:12   ` Marc Zyngier
2021-03-30 11:12     ` Suzuki K Poulose
2021-03-30 12:15       ` Marc Zyngier
2021-03-30 13:34         ` Suzuki K Poulose
2021-03-30 14:00           ` Marc Zyngier
2021-03-31 15:28       ` Alexandru Elisei
2021-03-31 15:37         ` Marc Zyngier
2021-03-23 12:06 ` [PATCH v5 08/19] coresight: etm4x: Move ETM to prohibited region for disable Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 09/19] coresight: etm-perf: Allow an event to use different sinks Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 10/19] coresight: Do not scan for graph if none is present Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 11/19] coresight: etm4x: Add support for PE OS lock Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 12/19] coresight: ete: Add support for ETE tracing Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 13/19] dts: bindings: Document device tree bindings for ETE Suzuki K Poulose
2021-03-23 22:46   ` Rob Herring
2021-03-23 12:06 ` [PATCH v5 14/19] coresight: etm-perf: Handle stale output handles Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 15/19] coresight: core: Add support for dedicated percpu sinks Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 16/19] coresight: sink: Add TRBE driver Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 17/19] Documentation: coresight: trbe: Sysfs ABI description Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 18/19] Documentation: trace: Add documentation for TRBE Suzuki K Poulose
2021-03-23 12:06 ` [PATCH v5 19/19] dts: bindings: Document device tree bindings for Arm TRBE Suzuki K Poulose
2021-03-23 16:33 ` (subset) [PATCH v5 00/19] coresight: Add support for ETE and TRBE Marc Zyngier
2021-03-23 16:34 ` Marc Zyngier
2021-03-23 17:05   ` Suzuki K Poulose

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=59aec851-e980-0a6d-8ba5-56a35fa5a7a9@arm.com \
    --to=suzuki.poulose@arm.com \
    --cc=anshuman.khandual@arm.com \
    --cc=catalin.marinas@arm.com \
    --cc=coresight@lists.linaro.org \
    --cc=leo.yan@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mathieu.poirier@linaro.org \
    --cc=maz@kernel.org \
    --cc=mike.leach@linaro.org \
    --cc=will.deacon@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

Powered by JetHome