Re: [PATCH v1 2/8] arm64: dts: qcom: sc7280: Add WSA SoundWire and LPASS support

[Prasad Kumpatla <quic_pkumpatl@quicinc.com>]

On 3/27/2025 4:32 AM, Bryan O'Donoghue wrote:
> On 17/03/2025 05:41, Prasad Kumpatla wrote:
>> From: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
>>
>> Add WSA macroLPASS Codecs along with SoundWire controller.
>>
>> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
>> Co-developed-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
>> Signed-off-by: Prasad Kumpatla <quic_pkumpatl@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/sc7280.dtsi | 68 ++++++++++++++++++++++++++++
>>   1 file changed, 68 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi 
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 39fbd3c40e47..90b2f6e2b7c0 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -2602,6 +2602,64 @@ swr1: soundwire@3230000 {
>>               status = "disabled";
>>           };
>>
>> +        lpass_wsa_macro: codec@3240000 {
>> +            compatible = "qcom,sc7280-lpass-wsa-macro";
>> +            reg = <0x0 0x03240000 0x0 0x1000>;
>> +
>> +            pinctrl-names = "default";
>> +            pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>;
>> +
>> +            clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>,
>> +                 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>,
>> +                 <&lpass_va_macro>;
>> +            clock-names = "mclk", "npl", "fsgen";
>
> clocks* go before pinctrl*
ACK,
>
>> +
>> +            power-domains = <&lpass_hm 
>> LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
>> +                    <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
>> +            power-domain-names = "macro", "dcodec";
>> +
>> +            #clock-cells = <0>;
>> +            clock-output-names = "mclk";
>> +            #sound-dai-cells = <1>;
>> +
>> +            status = "disabled";
>> +        };
>> +
>> +        swr2: soundwire@3250000 {
>> +            compatible = "qcom,soundwire-v1.6.0";
>> +            reg = <0x0 0x03250000 0x0 0x2000>;
>> +
>> +            interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
>> +            clocks = <&lpass_wsa_macro>;
>> +            clock-names = "iface";
>> +
>> +            qcom,din-ports = <2>;
>> +            qcom,dout-ports = <6>;
>> +
>> +            resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
>> +            reset-names = "swr_audio_cgcr";
>
> vendor prefixes should come after standard names
>
> Documentation/devicetree/bindings/dts-coding-style.rst
> "Order of Properties in Device Node"

ACK, will check and update in next patch version.

Thanks,
Prasad

>
>> +
>> +            qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07
>> +                                0x1f 0x3f 0x0f 0x0f>;
>> +            qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 
>> 0x0d 0x07 0x0a>;
>> +            qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 
>> 0x1f 0x00 0x00>;
>> +            qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 
>> 0xff 0xff 0xff>;
>> +            qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 
>> 0xff 0xff 0xff>;
>> +            qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 
>> 0xff 0xff 0xff 0xff>;
>> +            qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 
>> 0xff 0xff 0x01
>> +                                   0xff 0xff>;
>> +            qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 
>> 0xff 0xff 0xff
>> +                                0xff 0xff>;
>> +            qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 
>> 0xff 0xff
>> +                                0xff 0xff>;
>> +
>> +            #address-cells = <2>;
>> +            #size-cells = <0>;
>> +            #sound-dai-cells = <1>;
>> +
>> +            status = "disabled";
>> +        };
>> +
>>           lpass_audiocc: clock-controller@3300000 {
>>               compatible = "qcom,sc7280-lpassaudiocc";
>>               reg = <0 0x03300000 0 0x30000>,
>> @@ -2808,6 +2866,16 @@ lpass_tx_swr_data: tx-swr-data-state {
>>                   pins = "gpio1", "gpio2", "gpio14";
>>                   function = "swr_tx_data";
>>               };
>> +
>> +            lpass_wsa_swr_clk: wsa-swr-clk-state {
>> +                pins = "gpio10";
>> +                function = "wsa_swr_clk";
>> +            };
>> +
>> +            lpass_wsa_swr_data: wsa-swr-data-state {
>> +                pins = "gpio11";
>> +                function = "wsa_swr_data";
>> +            };
>>           };
>>
>>           gpu: gpu@3d00000 {
>> -- 
>> 2.34.1
>>
>>
>