* [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset
@ 2024-05-31 4:27 Linu Cherian
2024-05-31 4:27 ` [PATCH v8 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian
This patch series is rebased on v6.9.0.
Changelog from v7:
* Fixed breakage on perf test -vvvv "arm coresight".
No issues seen with and without "resrv" buffer mode
* Moved the crashdev registration into a seperate function.
* Removed redundant variable in tmc_etr_setup_crashdata_buf
* Avoided a redundant memcpy in tmc_panic_sync_etf.
* Tested kernel panic with trace session started uisng perf.
Please see the title "Perf based testing" below for details.
For this, stop_on_flush sysfs attribute is taken into
consideration while starting perf sessions as well.
Changelog from v6:
* Added special device files for reading crashdata, so that
read_prevboot mode flag is removed.
* Added new sysfs TMC device attribute, stop_on_flush.
Stop on flush trigger event is disabled by default.
User need to explicitly enable this from sysfs for panic stop
to work.
* Address parameter for panicstop ETM configuration is
chosen as kernel "panic" address by default.
* Added missing tmc_wait_for_tmcready during panic handling
* Few other misc code rearrangements.
Changelog from v5:
* Fixed issues reported by CONFIG_DEBUG_ATOMIC_SLEEP
* Fixed a memory leak while reading data from /dev/tmc_etrx in
READ_PREVBOOT mode
* Tested reading trace data from crashdump kernel
Changelog from v4:
* Device tree binding
- Description is made more explicit on the usage of reserved memory
region
- Mismatch in memory region names in dts binding and driver fixed
- Removed "mem" suffix from the memory region names
* Rename "struct tmc_register_snapshot" -> "struct tmc_crash_metadata",
since it contains more than register snapshot.
Related variables are named accordingly.
* Rename struct tmc_drvdata members
resrv_buf -> crash_tbuf
metadata -> crash_mdata
* Size field in metadata refers to RSZ register and hence indicates the
size in 32 bit words. ETR metadata follows this convention, the same
has been extended to ETF metadata as well.
* Added crc32 for more robust metadata and tracedata validation.
* Added/modified dev_dbg messages during metadata validation
* Fixed a typo in patch 5 commit description
Changelog from v3:
* Converted the Coresight ETM driver change to a named configuration.
RFC tag has been removed with this change.
* Fixed yaml issues reported by "make dt_binding_check"
* Added names for reserved memory regions 0 and 1
* Added prevalidation checks for metadata processing
* Fixed a regression introduced in RFC v3
- TMC Status register was getting saved wrongly
* Reverted memremap attribute changes from _WB to _WC to match
with the dma map attributes
* Introduced reserved buffer mode specific .sync op.
This fixes a possible crash when reserved buffer mode was used in
normal trace capture, due to unwanted dma maintenance operations.
v7 is posted here:
https://lore.kernel.org/lkml/20240307033625.325058-1-lcherian@marvell.com/
Using Coresight for Kernel panic and Watchdog reset
===================================================
This patch series is about extending Linux coresight driver support to
address kernel panic and watchdog reset scenarios. This would help
coresight users to debug kernel panic and watchdog reset using
coresight trace data.
Coresight trace capture: Kernel panic
-------------------------------------
From the coresight driver point of view, addressing the kernel panic
situation has four main requirements.
a. Support for allocation of trace buffer pages from reserved memory area.
Platform can advertise this using a new device tree property added to
relevant coresight nodes.
b. Support for stopping coresight blocks at the time of panic
c. Saving required metadata in the specified format
d. Support for reading trace data captured at the time of panic
Allocation of trace buffer pages from reserved RAM
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
A new optional device tree property "memory-region" is added to the
ETR/ETF device nodes, that would give the base address and size of trace
buffer.
Static allocation of trace buffers would ensure that both IOMMU enabled
and disabled cases are handled. Also, platforms that support persistent
RAM will allow users to read trace data in the subsequent boot without
booting the crashdump kernel.
Note:
For ETR sink devices, this reserved region will be used for both trace
capture and trace data retrieval.
For ETF sink devices, internal SRAM would be used for trace capture,
and they would be synced to reserved region for retrieval.
Note: Patches 1 & 2 adds support for this.
Disabling coresight blocks at the time of panic
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In order to avoid the situation of losing relevant trace data after a
kernel panic, it would be desirable to stop the coresight blocks at the
time of panic.
This can be achieved by configuring the comparator, CTI and sink
devices as below,
Comparator(triggers on kernel panic) --->External out --->CTI --
|
ETR/ETF stop <------External In <--------------
Note:
* Patch 6 provides the necessary ETR configuration.
* Patch 7 provides the necessary ETM configuration.
Saving metadata at the time of kernel panic
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Coresight metadata involves all additional data that are required for a
successful trace decode in addition to the trace data. This involves
ETR/ETF, ETE register snapshot etc.
A new optional device property "memory-region" is added to
the ETR/ETF/ETE device nodes for this.
Note: Patches 3 & 4 adds support for this.
Reading trace data captured at the time of panic
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Trace data captured at the time of panic, can be read from rebooted kernel
or from crashdump kernel using the below mentioned interface.
Note: Patch 5 adds support for this.
Steps for reading trace data captured in previous boot
++++++++++++++++++++++++++++++++++++++++++++++++++++++
1. cd /sys/bus/coresight/devices/tmc_etrXX/
2. Dump trace buffer crashdata to a file,
#dd if=/dev/crash_tmc_etrXX of=~/cstrace.bin
General flow of trace capture and decode incase of kernel panic
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1. Enable source and sink on all the cores using the sysfs interface.
ETR sink will have trace buffers allocated from reserved memory,
by selecting "resrv" buffer mode from sysfs.
2. Run relevant tests.
3. On a kernel panic, all coresight blocks are disabled, necessary
metadata is synced by kernel panic handler.
System would eventually reboot or boot a crashdump kernel.
4. For platforms that supports crashdump kernel, raw trace data can be
dumped using the coresight sysfs interface from the crashdump kernel
itself. Persistent RAM is not a requirement in this case.
5. For platforms that supports persistent RAM, trace data can be dumped
using the coresight sysfs interface in the subsequent Linux boot.
Crashdump kernel is not a requirement in this case. Persistent RAM
ensures that trace data is intact across reboot.
Coresight trace capture: Watchdog reset
---------------------------------------
The main difference between addressing the watchdog reset and kernel panic
case are below,
a. Saving coresight metadata need to be taken care by the
SCP(system control processor) firmware in the specified format,
instead of kernel.
b. Reserved memory region given by firmware for trace buffer and metadata
has to be in persistent RAM.
Note: This is a requirement for watchdog reset case but optional
in kernel panic case.
Watchdog reset can be supported only on platforms that meet the above
two requirements.
Testing Kernel panic on Linux 6.8
---------------------------------
1. Enable the preloaded ETM configuration
#echo 1 > /sys/kernel/config/cs-syscfg/configurations/panicstop/enable
2. Configure CTI using sysfs interface
#./cti_setup.sh
#cat cti_setup.sh
cd /sys/bus/coresight/devices/
ap_cti_config () {
#ETM trig out[0] trigger to Channel 0
echo 0 4 > channels/trigin_attach
}
etf_cti_config () {
#ETF Flush in trigger from Channel 0
echo 0 1 > channels/trigout_attach
echo 1 > channels/trig_filter_enable
}
etr_cti_config () {
#ETR Flush in from Channel 0
echo 0 1 > channels/trigout_attach
echo 1 > channels/trig_filter_enable
}
ctidevs=`find . -name "cti*"`
for i in $ctidevs
do
cd $i
connection=`find . -name "ete*"`
if [ ! -z "$connection" ]
then
echo "AP CTI config for $i"
ap_cti_config
fi
connection=`find . -name "tmc_etf*"`
if [ ! -z "$connection" ]
then
echo "ETF CTI config for $i"
etf_cti_config
fi
connection=`find . -name "tmc_etr*"`
if [ ! -z "$connection" ]
then
echo "ETR CTI config for $i"
etr_cti_config
fi
cd ..
done
Note: CTI connections are SOC specific and hence the above script is
added just for reference.
3. Choose reserved buffer mode for ETR buffer
#echo "resrv" > /sys/bus/coresight/devices/tmc_etr0/buf_mode_preferred
4. Enable stop on flush trigger configuration
#echo 1 > /sys/bus/coresight/devices/tmc_etr0/stop_on_flush
4. Start Coresight tracing on cores 1 and 2 using sysfs interface
5. Run some application on core 1
#taskset -c 1 dd if=/dev/urandom of=/dev/null &
6. Invoke kernel panic on core 2
#echo 1 > /proc/sys/kernel/panic
#taskset -c 2 echo c > /proc/sysrq-trigger
7. From rebooted kernel or crashdump kernel, read crashdata
Note: For crashdump kernel option, please make sure "crash_kexec_post_notifiers" is
added to the kernel bootargs.
#dd if=/dev/crash_tmc_etr0 of=/trace/cstrace.bin
8. Run opencsd decoder tools/scripts to generate the instruction trace.
Sample Core 1 instruction trace dump:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
A etm4_enable_hw: ffff800008ae1dd4
CONTEXT EL2 etm4_enable_hw: ffff800008ae1dd4
I etm4_enable_hw: ffff800008ae1dd4:
d503201f nop
I etm4_enable_hw: ffff800008ae1dd8:
d503201f nop
I etm4_enable_hw: ffff800008ae1ddc:
d503201f nop
I etm4_enable_hw: ffff800008ae1de0:
d503201f nop
I etm4_enable_hw: ffff800008ae1de4:
d503201f nop
I etm4_enable_hw: ffff800008ae1de8:
d503233f paciasp
I etm4_enable_hw: ffff800008ae1dec:
a9be7bfd stp x29, x30, [sp, #-32]!
I etm4_enable_hw: ffff800008ae1df0:
910003fd mov x29, sp
I etm4_enable_hw: ffff800008ae1df4:
a90153f3 stp x19, x20, [sp, #16]
I etm4_enable_hw: ffff800008ae1df8:
2a0003f4 mov w20, w0
I etm4_enable_hw: ffff800008ae1dfc:
900085b3 adrp x19, ffff800009b95000 <reserved_mem+0xc48>
I etm4_enable_hw: ffff800008ae1e00:
910f4273 add x19, x19, #0x3d0
I etm4_enable_hw: ffff800008ae1e04:
f8747a60 ldr x0, [x19, x20, lsl #3]
E etm4_enable_hw: ffff800008ae1e08:
b4000140 cbz x0, ffff800008ae1e30 <etm4_starting_cpu+0x50>
I 149.039572921 etm4_enable_hw: ffff800008ae1e30:
a94153f3 ldp x19, x20, [sp, #16]
I 149.039572921 etm4_enable_hw: ffff800008ae1e34:
52800000 mov w0, #0x0 // #0
I 149.039572921 etm4_enable_hw: ffff800008ae1e38:
a8c27bfd ldp x29, x30, [sp], #32
..snip
149.052324811 chacha_block_generic: ffff800008642d80:
9100a3e0 add x0,
I 149.052324811 chacha_block_generic: ffff800008642d84:
b86178a2 ldr w2, [x5, x1, lsl #2]
I 149.052324811 chacha_block_generic: ffff800008642d88:
8b010803 add x3, x0, x1, lsl #2
I 149.052324811 chacha_block_generic: ffff800008642d8c:
b85fc063 ldur w3, [x3, #-4]
I 149.052324811 chacha_block_generic: ffff800008642d90:
0b030042 add w2, w2, w3
I 149.052324811 chacha_block_generic: ffff800008642d94:
b8217882 str w2, [x4, x1, lsl #2]
I 149.052324811 chacha_block_generic: ffff800008642d98:
91000421 add x1, x1, #0x1
I 149.052324811 chacha_block_generic: ffff800008642d9c:
f100443f cmp x1, #0x11
Sample Core 2 instruction trace dump(kernel panic triggered core):
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
A etm4_enable_hw: ffff800008ae1dd4
CONTEXT EL2 etm4_enable_hw: ffff800008ae1dd4
I etm4_enable_hw: ffff800008ae1dd4:
d503201f nop
I etm4_enable_hw: ffff800008ae1dd8:
d503201f nop
I etm4_enable_hw: ffff800008ae1ddc:
d503201f nop
I etm4_enable_hw: ffff800008ae1de0:
d503201f nop
I etm4_enable_hw: ffff800008ae1de4:
d503201f nop
I etm4_enable_hw: ffff800008ae1de8:
d503233f paciasp
I etm4_enable_hw: ffff800008ae1dec:
a9be7bfd stp x29, x30, [sp, #-32]!
I etm4_enable_hw: ffff800008ae1df0:
910003fd mov x29, sp
I etm4_enable_hw: ffff800008ae1df4:
a90153f3 stp x19, x20, [sp, #16]
I etm4_enable_hw: ffff800008ae1df8:
2a0003f4 mov w20, w0
I etm4_enable_hw: ffff800008ae1dfc:
900085b3 adrp x19, ffff800009b95000 <reserved_mem+0xc48>
I etm4_enable_hw: ffff800008ae1e00:
910f4273 add x19, x19, #0x3d0
I etm4_enable_hw: ffff800008ae1e04:
f8747a60 ldr x0, [x19, x20, lsl #3]
E etm4_enable_hw: ffff800008ae1e08:
b4000140 cbz x0, ffff800008ae1e30 <etm4_starting_cpu+0x50>
I 149.046243445 etm4_enable_hw: ffff800008ae1e30:
a94153f3 ldp x19, x20, [sp, #16]
I 149.046243445 etm4_enable_hw: ffff800008ae1e34:
52800000 mov w0, #0x0 // #0
I 149.046243445 etm4_enable_hw: ffff800008ae1e38:
a8c27bfd ldp x29, x30, [sp], #32
I 149.046243445 etm4_enable_hw: ffff800008ae1e3c:
d50323bf autiasp
E 149.046243445 etm4_enable_hw: ffff800008ae1e40:
d65f03c0 ret
A ete_sysreg_write: ffff800008adfa18
..snip
I 149.05422547 panic: ffff800008096300:
a90363f7 stp x23, x24, [sp, #48]
I 149.05422547 panic: ffff800008096304:
6b00003f cmp w1, w0
I 149.05422547 panic: ffff800008096308:
3a411804 ccmn w0, #0x1, #0x4, ne // ne = any
N 149.05422547 panic: ffff80000809630c:
540001e0 b.eq ffff800008096348 <panic+0xe0> // b.none
I 149.05422547 panic: ffff800008096310:
f90023f9 str x25, [sp, #64]
E 149.05422547 panic: ffff800008096314:
97fe44ef bl ffff8000080276d0 <panic_smp_self_stop>
A panic: ffff80000809634c
I 149.05422547 panic: ffff80000809634c:
910102d5 add x21, x22, #0x40
I 149.05422547 panic: ffff800008096350:
52800020 mov w0, #0x1 // #1
E 149.05422547 panic: ffff800008096354:
94166b8b bl ffff800008631180 <bust_spinlocks>
N 149.054225518 bust_spinlocks: ffff800008631180:
340000c0 cbz w0, ffff800008631198 <bust_spinlocks+0x18>
I 149.054225518 bust_spinlocks: ffff800008631184:
f000a321 adrp x1, ffff800009a98000 <pbufs.0+0xbb8>
I 149.054225518 bust_spinlocks: ffff800008631188:
b9405c20 ldr w0, [x1, #92]
I 149.054225518 bust_spinlocks: ffff80000863118c:
11000400 add w0, w0, #0x1
I 149.054225518 bust_spinlocks: ffff800008631190:
b9005c20 str w0, [x1, #92]
E 149.054225518 bust_spinlocks: ffff800008631194:
d65f03c0 ret
A panic: ffff800008096358
Perf based testing
------------------
Kernel panic during perf trace sessions has been tested with this series.
Starting perf session
~~~~~~~~~~~~~~~~~~~~~
ETF:
./tools/perf/perf record -e cs_etm/panicstop,@tmc_etf1/ -C 1
./tools/perf/perf record -e cs_etm/panicstop,@tmc_etf2/ -C 2
ETR:
./tools/perf/perf record -e cs_etm/panicstop,@tmc_etr0/ -C 1,2
Reading trace data after panic
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Same sysfs based method explained above can be used to retrieve and
decode the trace data after the reboot on kernel panic.
Future Improvements
-------------------
* Explore changing CTI sysfs script to system configuration manager profile
Linu Cherian (7):
dt-bindings: arm: coresight-tmc: Add "memory-region" property
coresight: tmc-etr: Add support to use reserved trace memory
coresight: core: Add provision for panic callbacks
coresight: tmc: Enable panic sync handling
coresight: tmc: Add support for reading crash data
coresight: tmc: Stop trace capture on FlIn
coresight: config: Add preloaded configuration
.../bindings/arm/arm,coresight-tmc.yaml | 26 ++
drivers/hwtracing/coresight/Makefile | 2 +-
.../coresight/coresight-cfg-preload.c | 2 +
.../coresight/coresight-cfg-preload.h | 2 +
.../hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++
drivers/hwtracing/coresight/coresight-core.c | 37 ++
.../coresight/coresight-etm4x-core.c | 1 +
.../hwtracing/coresight/coresight-tmc-core.c | 251 +++++++++++++-
.../hwtracing/coresight/coresight-tmc-etf.c | 163 ++++++++-
.../hwtracing/coresight/coresight-tmc-etr.c | 319 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 83 +++++
include/linux/coresight.h | 25 ++
12 files changed, 977 insertions(+), 17 deletions(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 4:27 ` [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
` (5 subsequent siblings)
6 siblings, 0 replies; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian, Rob Herring
memory-region 0: Reserved trace buffer memory
TMC ETR: When available, use this reserved memory region for
trace data capture. Same region is used for trace data
retention after a panic or watchdog reset.
TMC ETF: When available, use this reserved memory region for
trace data retention synced from internal SRAM after a panic or
watchdog reset.
memory-region 1: Reserved meta data memory
TMC ETR, ETF: When available, use this memory for register
snapshot retention synced from hardware registers after a panic
or watchdog reset.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
.../bindings/arm/arm,coresight-tmc.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
index cb8dceaca70e..4787d7c6bac2 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
@@ -101,6 +101,29 @@ properties:
and ETF configurations.
$ref: /schemas/graph.yaml#/properties/port
+ memory-region:
+ items:
+ - description: Reserved trace buffer memory for ETR and ETF sinks.
+ For ETR, this reserved memory region is used for trace data capture.
+ Same region is used for trace data retention as well after a panic
+ or watchdog reset.
+ This reserved memory region is used as trace buffer or used for trace
+ data retention only if specifically selected by the user in sysfs
+ interface.
+ The default memory usage models for ETR in sysfs/perf modes are
+ otherwise unaltered.
+
+ For ETF, this reserved memory region is used by default for
+ retention of trace data synced from internal SRAM after a panic
+ or watchdog reset.
+ - description: Reserved meta data memory. Used for ETR and ETF sinks
+ for storing metadata.
+
+ memory-region-names:
+ items:
+ - const: tracedata
+ - const: metadata
+
required:
- compatible
- reg
@@ -115,6 +138,9 @@ examples:
etr@20070000 {
compatible = "arm,coresight-tmc", "arm,primecell";
reg = <0x20070000 0x1000>;
+ memory-region = <&etr_trace_mem_reserved>,
+ <&etr_mdata_mem_reserved>;
+ memory-region-names = "tracedata", "metadata";
clocks = <&oscclk6a>;
clock-names = "apb_pclk";
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-05-31 4:27 ` [PATCH v8 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:05 ` James Clark
2024-05-31 4:27 ` [PATCH v8 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
` (4 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian, Anil Kumar Reddy
Add support to use reserved memory for coresight ETR trace buffer.
Introduce a new ETR buffer mode called ETR_MODE_RESRV, which
becomes available when ETR device tree node is supplied with a valid
reserved memory region.
ETR_MODE_RESRV can be selected only by explicit user request.
$ echo resrv >/sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
Changelog from v7:
* Reverted all changes in tmc_alloc_etr_buf that has creeped in by mistake
during refactoring. This fixes the "perf test" breakage.
.../hwtracing/coresight/coresight-tmc-core.c | 47 +++++++++++
.../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 27 +++++++
3 files changed, 153 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 72005b0c633e..1325387d6257 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -22,6 +22,7 @@
#include <linux/spinlock.h>
#include <linux/pm_runtime.h>
#include <linux/of.h>
+#include <linux/of_address.h>
#include <linux/coresight.h>
#include <linux/amba/bus.h>
@@ -370,6 +371,50 @@ static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
return (auth & TMC_AUTH_NSID_MASK) == 0x3;
}
+static struct device_node *tmc_get_region_byname(struct device_node *node,
+ char *name)
+{
+ int index;
+
+ index = of_property_match_string(node, "memory-region-names", name);
+ if (index < 0)
+ return ERR_PTR(-ENODEV);
+
+ return of_parse_phandle(node, "memory-region", index);
+}
+
+static void tmc_get_reserved_region(struct device *parent)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
+ struct device_node *node;
+ struct resource res;
+ int rc;
+
+ node = tmc_get_region_byname(parent->of_node, "tracedata");
+ if (IS_ERR_OR_NULL(node)) {
+ dev_dbg(parent, "No reserved trace buffer specified\n");
+ return;
+ }
+
+ rc = of_address_to_resource(node, 0, &res);
+ of_node_put(node);
+ if (rc || res.start == 0 || resource_size(&res) == 0) {
+ dev_err(parent, "Reserved trace buffer memory is invalid\n");
+ return;
+ }
+
+ drvdata->crash_tbuf.vaddr = memremap(res.start,
+ resource_size(&res),
+ MEMREMAP_WC);
+ if (IS_ERR_OR_NULL(drvdata->crash_tbuf.vaddr)) {
+ dev_err(parent, "Reserved trace buffer mapping failed\n");
+ return;
+ }
+
+ drvdata->crash_tbuf.paddr = res.start;
+ drvdata->crash_tbuf.size = resource_size(&res);
+}
+
/* Detect and initialise the capabilities of a TMC ETR */
static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
{
@@ -482,6 +527,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
}
+ tmc_get_reserved_region(dev);
+
desc.dev = dev;
switch (drvdata->config_type) {
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index e75428fa1592..041c428dd7cd 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -30,6 +30,7 @@ struct etr_buf_hw {
bool has_iommu;
bool has_etr_sg;
bool has_catu;
+ bool has_resrv;
};
/*
@@ -694,6 +695,75 @@ static const struct etr_buf_operations etr_flat_buf_ops = {
.get_data = tmc_etr_get_data_flat_buf,
};
+/*
+ * tmc_etr_alloc_resrv_buf: Allocate a contiguous DMA buffer from reserved region.
+ */
+static int tmc_etr_alloc_resrv_buf(struct tmc_drvdata *drvdata,
+ struct etr_buf *etr_buf, int node,
+ void **pages)
+{
+ struct etr_flat_buf *resrv_buf;
+ struct device *real_dev = drvdata->csdev->dev.parent;
+
+ /* We cannot reuse existing pages for resrv buf */
+ if (pages)
+ return -EINVAL;
+
+ resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_KERNEL);
+ if (!resrv_buf)
+ return -ENOMEM;
+
+ resrv_buf->daddr = dma_map_resource(real_dev, drvdata->crash_tbuf.paddr,
+ drvdata->crash_tbuf.size,
+ DMA_FROM_DEVICE, 0);
+ if (dma_mapping_error(real_dev, resrv_buf->daddr)) {
+ dev_err(real_dev, "failed to map source buffer address\n");
+ kfree(resrv_buf);
+ return -ENOMEM;
+ }
+
+ resrv_buf->vaddr = drvdata->crash_tbuf.vaddr;
+ resrv_buf->size = etr_buf->size = drvdata->crash_tbuf.size;
+ resrv_buf->dev = &drvdata->csdev->dev;
+ etr_buf->hwaddr = resrv_buf->daddr;
+ etr_buf->mode = ETR_MODE_RESRV;
+ etr_buf->private = resrv_buf;
+ return 0;
+}
+
+static void tmc_etr_free_resrv_buf(struct etr_buf *etr_buf)
+{
+ struct etr_flat_buf *resrv_buf = etr_buf->private;
+
+ if (resrv_buf && resrv_buf->daddr) {
+ struct device *real_dev = resrv_buf->dev->parent;
+
+ dma_unmap_resource(real_dev, resrv_buf->daddr,
+ resrv_buf->size, DMA_FROM_DEVICE, 0);
+ }
+ kfree(resrv_buf);
+}
+
+static void tmc_etr_sync_resrv_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
+{
+ /*
+ * Adjust the buffer to point to the beginning of the trace data
+ * and update the available trace data.
+ */
+ etr_buf->offset = rrp - etr_buf->hwaddr;
+ if (etr_buf->full)
+ etr_buf->len = etr_buf->size;
+ else
+ etr_buf->len = rwp - rrp;
+}
+
+static const struct etr_buf_operations etr_resrv_buf_ops = {
+ .alloc = tmc_etr_alloc_resrv_buf,
+ .free = tmc_etr_free_resrv_buf,
+ .sync = tmc_etr_sync_resrv_buf,
+ .get_data = tmc_etr_get_data_flat_buf,
+};
+
/*
* tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters
* appropriately.
@@ -800,6 +870,7 @@ static const struct etr_buf_operations *etr_buf_ops[] = {
[ETR_MODE_FLAT] = &etr_flat_buf_ops,
[ETR_MODE_ETR_SG] = &etr_sg_buf_ops,
[ETR_MODE_CATU] = NULL,
+ [ETR_MODE_RESRV] = &etr_resrv_buf_ops
};
void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu)
@@ -825,6 +896,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode,
case ETR_MODE_FLAT:
case ETR_MODE_ETR_SG:
case ETR_MODE_CATU:
+ case ETR_MODE_RESRV:
if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc)
rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf,
node, pages);
@@ -843,6 +915,7 @@ static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw)
buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent);
buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);
buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata);
+ buf_hw->has_resrv = is_tmc_reserved_region_valid(dev->parent);
}
static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size)
@@ -1830,6 +1903,7 @@ static const char *const buf_modes_str[] = {
[ETR_MODE_FLAT] = "flat",
[ETR_MODE_ETR_SG] = "tmc-sg",
[ETR_MODE_CATU] = "catu",
+ [ETR_MODE_RESRV] = "resrv",
[ETR_MODE_AUTO] = "auto",
};
@@ -1848,6 +1922,9 @@ static ssize_t buf_modes_available_show(struct device *dev,
if (buf_hw.has_catu)
size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]);
+ if (buf_hw.has_resrv)
+ size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_RESRV]);
+
size += sysfs_emit_at(buf, size, "\n");
return size;
}
@@ -1875,6 +1952,8 @@ static ssize_t buf_mode_preferred_store(struct device *dev,
drvdata->etr_mode = ETR_MODE_ETR_SG;
else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_catu)
drvdata->etr_mode = ETR_MODE_CATU;
+ else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_RESRV]) && buf_hw.has_resrv)
+ drvdata->etr_mode = ETR_MODE_RESRV;
else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO]))
drvdata->etr_mode = ETR_MODE_AUTO;
else
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index cef979c897e6..2abc5387cdf7 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -135,6 +135,7 @@ enum etr_mode {
ETR_MODE_FLAT, /* Uses contiguous flat buffer */
ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
ETR_MODE_CATU, /* Use SG mechanism in CATU */
+ ETR_MODE_RESRV, /* Use reserved region contiguous buffer */
ETR_MODE_AUTO, /* Use the default mechanism */
};
@@ -164,6 +165,17 @@ struct etr_buf {
void *private;
};
+/**
+ * @paddr : Start address of reserved memory region.
+ * @vaddr : Corresponding CPU virtual address.
+ * @size : Size of reserved memory region.
+ */
+struct tmc_resrv_buf {
+ phys_addr_t paddr;
+ void *vaddr;
+ size_t size;
+};
+
/**
* struct tmc_drvdata - specifics associated to an TMC component
* @base: memory mapped base address for this component.
@@ -187,6 +199,10 @@ struct etr_buf {
* @idr_mutex: Access serialisation for idr.
* @sysfs_buf: SYSFS buffer for ETR.
* @perf_buf: PERF buffer for ETR.
+ * @crash_tbuf: Used by ETR as hardware trace buffer and for trace data
+ * retention (after crash) only when ETR_MODE_RESRV buffer
+ * mode is enabled. Used by ETF for trace data retention
+ * (after crash) by default.
*/
struct tmc_drvdata {
void __iomem *base;
@@ -211,6 +227,7 @@ struct tmc_drvdata {
struct mutex idr_mutex;
struct etr_buf *sysfs_buf;
struct etr_buf *perf_buf;
+ struct tmc_resrv_buf crash_tbuf;
};
struct etr_buf_operations {
@@ -328,6 +345,16 @@ tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;
}
+static inline bool is_tmc_reserved_region_valid(struct device *dev)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
+
+ if (drvdata->crash_tbuf.paddr &&
+ drvdata->crash_tbuf.size)
+ return true;
+ return false;
+}
+
struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 3/7] coresight: core: Add provision for panic callbacks
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-05-31 4:27 ` [PATCH v8 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2024-05-31 4:27 ` [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:07 ` James Clark
2024-05-31 4:27 ` [PATCH v8 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
` (3 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian
Panic callback handlers allows coresight device drivers to sync
relevant trace data and trace metadata to reserved memory
regions so that they can be retrieved later in the subsequent
boot or in the crashdump kernel.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++++++++
include/linux/coresight.h | 12 +++++++
2 files changed, 49 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index b83613e34289..61d75aad476b 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -19,6 +19,7 @@
#include <linux/property.h>
#include <linux/delay.h>
#include <linux/pm_runtime.h>
+#include <linux/panic_notifier.h>
#include "coresight-etm-perf.h"
#include "coresight-priv.h"
@@ -1365,6 +1366,36 @@ const struct bus_type coresight_bustype = {
.name = "coresight",
};
+static int coresight_panic_sync(struct device *dev, void *data)
+{
+ int mode;
+ struct coresight_device *csdev;
+
+ /* Run through panic sync handlers for all enabled devices */
+ csdev = container_of(dev, struct coresight_device, dev);
+ mode = coresight_get_mode(csdev);
+
+ if ((mode == CS_MODE_SYSFS) || (mode == CS_MODE_PERF)) {
+ if (panic_ops(csdev))
+ panic_ops(csdev)->sync(csdev);
+ }
+
+ return 0;
+}
+
+static int coresight_panic_cb(struct notifier_block *self,
+ unsigned long v, void *p)
+{
+ bus_for_each_dev(&coresight_bustype, NULL, NULL,
+ coresight_panic_sync);
+
+ return 0;
+}
+
+static struct notifier_block coresight_notifier = {
+ .notifier_call = coresight_panic_cb,
+};
+
static int __init coresight_init(void)
{
int ret;
@@ -1377,6 +1408,10 @@ static int __init coresight_init(void)
if (ret)
goto exit_bus_unregister;
+ /* Register function to be called for panic */
+ ret = atomic_notifier_chain_register(&panic_notifier_list,
+ &coresight_notifier);
+
/* initialise the coresight syscfg API */
ret = cscfg_init();
if (!ret)
@@ -1391,6 +1426,8 @@ static int __init coresight_init(void)
static void __exit coresight_exit(void)
{
cscfg_exit();
+ atomic_notifier_chain_unregister(&panic_notifier_list,
+ &coresight_notifier);
etm_perf_exit();
bus_unregister(&coresight_bustype);
}
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 5f288d475490..b156467c9baa 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -315,6 +315,7 @@ enum cs_mode {
#define link_ops(csdev) csdev->ops->link_ops
#define helper_ops(csdev) csdev->ops->helper_ops
#define ect_ops(csdev) csdev->ops->ect_ops
+#define panic_ops(csdev) csdev->ops->panic_ops
/**
* struct coresight_ops_sink - basic operations for a sink
@@ -384,11 +385,22 @@ struct coresight_ops_helper {
int (*disable)(struct coresight_device *csdev, void *data);
};
+
+/**
+ * struct coresight_ops_panic - Generic device ops for panic handing
+ *
+ * @sync : Sync the device register state/trace data
+ */
+struct coresight_ops_panic {
+ int (*sync)(struct coresight_device *csdev);
+};
+
struct coresight_ops {
const struct coresight_ops_sink *sink_ops;
const struct coresight_ops_link *link_ops;
const struct coresight_ops_source *source_ops;
const struct coresight_ops_helper *helper_ops;
+ const struct coresight_ops_panic *panic_ops;
};
static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 4/7] coresight: tmc: Enable panic sync handling
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
` (2 preceding siblings ...)
2024-05-31 4:27 ` [PATCH v8 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:10 ` James Clark
2024-05-31 4:27 ` [PATCH v8 5/7] coresight: tmc: Add support for reading crash data Linu Cherian
` (2 subsequent siblings)
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian
- Get reserved region from device tree node for metadata
- Define metadata format for TMC
- Add TMC ETR panic sync handler that syncs register snapshot
to metadata region
- Add TMC ETF panic sync handler that syncs register snapshot
to metadata region and internal SRAM to reserved trace buffer
region.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
Changelog from v7:
Avoided a redundant memcpy in tmc_panic_sync_etf.
.../hwtracing/coresight/coresight-tmc-core.c | 25 +++++++
.../hwtracing/coresight/coresight-tmc-etf.c | 72 +++++++++++++++++++
.../hwtracing/coresight/coresight-tmc-etr.c | 70 ++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 45 +++++++++++-
4 files changed, 211 insertions(+), 1 deletion(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 1325387d6257..7170416c3e1a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -413,6 +413,31 @@ static void tmc_get_reserved_region(struct device *parent)
drvdata->crash_tbuf.paddr = res.start;
drvdata->crash_tbuf.size = resource_size(&res);
+
+ /* Metadata region */
+ node = tmc_get_region_byname(parent->of_node, "metadata");
+ if (IS_ERR_OR_NULL(node)) {
+ dev_dbg(parent, "No metadata memory-region specified\n");
+ return;
+ }
+
+ rc = of_address_to_resource(node, 0, &res);
+ of_node_put(node);
+ if (rc || res.start == 0 || resource_size(&res) == 0) {
+ dev_err(parent, "Metadata memory is invalid\n");
+ return;
+ }
+
+ drvdata->crash_mdata.vaddr = memremap(res.start,
+ resource_size(&res),
+ MEMREMAP_WC);
+ if (IS_ERR_OR_NULL(drvdata->crash_mdata.vaddr)) {
+ dev_err(parent, "Metadata memory mapping failed\n");
+ return;
+ }
+
+ drvdata->crash_mdata.paddr = res.start;
+ drvdata->crash_mdata.size = resource_size(&res);
}
/* Detect and initialise the capabilities of a TMC ETR */
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index d4f641cd9de6..f9569585e9f8 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -590,6 +590,73 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
return to_read;
}
+static int tmc_panic_sync_etf(struct coresight_device *csdev)
+{
+ u32 val;
+ struct csdev_access *csa;
+ struct tmc_crash_metadata *mdata;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ csa = &drvdata->csdev->access;
+
+ /* Make sure we have valid reserved memory */
+ if (!is_tmc_reserved_region_valid(csdev->dev.parent))
+ return 0;
+
+ mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
+ mdata->valid = false;
+
+ CS_UNLOCK(drvdata->base);
+
+ /* Proceed only if ETF is enabled or configured as sink */
+ val = readl(drvdata->base + TMC_CTL);
+ if (!(val & TMC_CTL_CAPT_EN))
+ goto out;
+
+ val = readl(drvdata->base + TMC_MODE);
+ if (val != TMC_MODE_CIRCULAR_BUFFER)
+ goto out;
+
+ val = readl(drvdata->base + TMC_FFSR);
+ /* Do manual flush and stop only if its not auto-stopped */
+ if (!(val & TMC_FFSR_FT_STOPPED)) {
+ dev_info(&csdev->dev,
+ "%s: Triggering manual flush\n", __func__);
+ tmc_flush_and_stop(drvdata);
+ } else
+ tmc_wait_for_tmcready(drvdata);
+
+ /* Sync registers from hardware to metadata region */
+ mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS);
+ mdata->trc_paddr = drvdata->crash_tbuf.paddr;
+
+ /* Sync Internal SRAM to reserved trace buffer region */
+ drvdata->buf = drvdata->crash_tbuf.vaddr;
+ tmc_etb_dump_hw(drvdata);
+ /* Store as per RSZ register convention */
+ mdata->size = drvdata->len >> 2;
+
+ /*
+ * Make sure all previous writes are completed,
+ * before we mark valid
+ */
+ dsb(sy);
+ mdata->valid = true;
+ /*
+ * Below order need to maintained, since crc of metadata
+ * is dependent on first
+ */
+ mdata->crc32_tdata = find_crash_tracedata_crc(drvdata, mdata);
+ mdata->crc32_mdata = find_crash_metadata_crc(mdata);
+
+ tmc_disable_hw(drvdata);
+
+ dev_info(&csdev->dev, "%s: success\n", __func__);
+out:
+ CS_UNLOCK(drvdata->base);
+ return 0;
+}
+
static const struct coresight_ops_sink tmc_etf_sink_ops = {
.enable = tmc_enable_etf_sink,
.disable = tmc_disable_etf_sink,
@@ -603,6 +670,10 @@ static const struct coresight_ops_link tmc_etf_link_ops = {
.disable = tmc_disable_etf_link,
};
+static const struct coresight_ops_panic tmc_etf_sync_ops = {
+ .sync = tmc_panic_sync_etf,
+};
+
const struct coresight_ops tmc_etb_cs_ops = {
.sink_ops = &tmc_etf_sink_ops,
};
@@ -610,6 +681,7 @@ const struct coresight_ops tmc_etb_cs_ops = {
const struct coresight_ops tmc_etf_cs_ops = {
.sink_ops = &tmc_etf_sink_ops,
.link_ops = &tmc_etf_link_ops,
+ .panic_ops = &tmc_etf_sync_ops,
};
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 041c428dd7cd..be1079e8fd64 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1813,6 +1813,71 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
return 0;
}
+static int tmc_panic_sync_etr(struct coresight_device *csdev)
+{
+ u32 val;
+ struct csdev_access *csa;
+ struct tmc_crash_metadata *mdata;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ csa = &drvdata->csdev->access;
+
+ if (!drvdata->etr_buf)
+ return 0;
+
+ /* Being in RESRV mode implies valid reserved memory as well */
+ if (drvdata->etr_buf->mode != ETR_MODE_RESRV)
+ return 0;
+
+ mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
+ mdata->valid = false;
+
+ CS_UNLOCK(drvdata->base);
+
+ /* Proceed only if ETR is enabled */
+ val = readl(drvdata->base + TMC_CTL);
+ if (!(val & TMC_CTL_CAPT_EN))
+ goto out;
+
+ val = readl(drvdata->base + TMC_FFSR);
+ /* Do manual flush and stop only if its not auto-stopped */
+ if (!(val & TMC_FFSR_FT_STOPPED)) {
+ dev_info(&csdev->dev,
+ "%s: Triggering manual flush\n", __func__);
+ tmc_flush_and_stop(drvdata);
+ } else
+ tmc_wait_for_tmcready(drvdata);
+
+ /* Sync registers from hardware to metadata region */
+ mdata->size = csdev_access_relaxed_read32(csa, TMC_RSZ);
+ mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS);
+ mdata->rrp = tmc_read_rrp(drvdata);
+ mdata->rwp = tmc_read_rwp(drvdata);
+ mdata->dba = tmc_read_dba(drvdata);
+ mdata->trc_paddr = drvdata->crash_tbuf.paddr;
+
+ /*
+ * Make sure all previous writes are completed,
+ * before we mark valid
+ */
+ dsb(sy);
+ mdata->valid = true;
+ /*
+ * Below order need to maintained, since crc of metadata
+ * is dependent on first
+ */
+ mdata->crc32_tdata = find_crash_tracedata_crc(drvdata, mdata);
+ mdata->crc32_mdata = find_crash_metadata_crc(mdata);
+
+ tmc_disable_hw(drvdata);
+
+ dev_info(&csdev->dev, "%s: success\n", __func__);
+out:
+ CS_UNLOCK(drvdata->base);
+
+ return 0;
+}
+
static const struct coresight_ops_sink tmc_etr_sink_ops = {
.enable = tmc_enable_etr_sink,
.disable = tmc_disable_etr_sink,
@@ -1821,8 +1886,13 @@ static const struct coresight_ops_sink tmc_etr_sink_ops = {
.free_buffer = tmc_free_etr_buffer,
};
+static const struct coresight_ops_panic tmc_etr_sync_ops = {
+ .sync = tmc_panic_sync_etr,
+};
+
const struct coresight_ops tmc_etr_cs_ops = {
.sink_ops = &tmc_etr_sink_ops,
+ .panic_ops = &tmc_etr_sync_ops,
};
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 2abc5387cdf7..875d4129da7c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -12,6 +12,7 @@
#include <linux/miscdevice.h>
#include <linux/mutex.h>
#include <linux/refcount.h>
+#include <linux/crc32.h>
#define TMC_RSZ 0x004
#define TMC_STS 0x00c
@@ -76,6 +77,9 @@
#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
+/* TMC_FFSR - 0x300 */
+#define TMC_FFSR_FT_STOPPED BIT(1)
+
/* TMC_FFCR - 0x304 */
#define TMC_FFCR_FLUSHMAN_BIT 6
#define TMC_FFCR_EN_FMT BIT(0)
@@ -131,6 +135,21 @@ enum tmc_mem_intf_width {
#define CORESIGHT_SOC_600_ETR_CAPS \
(TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
+/* TMC metadata region for ETR and ETF configurations */
+struct tmc_crash_metadata {
+ uint32_t crc32_mdata; /* crc of metadata */
+ uint32_t crc32_tdata; /* crc of tracedata */
+ uint32_t valid; /* Indicate if this ETF/ETR was enabled */
+ uint32_t size; /* Ram Size register */
+ uint32_t sts; /* Status register */
+ uint32_t reserved32[3];
+ uint64_t rrp; /* Ram Read pointer register */
+ uint64_t rwp; /* Ram Write pointer register */
+ uint64_t dba; /* Data buffer address register */
+ uint64_t trc_paddr; /* Phys address of trace buffer */
+ uint64_t reserved64[3];
+};
+
enum etr_mode {
ETR_MODE_FLAT, /* Uses contiguous flat buffer */
ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
@@ -203,6 +222,8 @@ struct tmc_resrv_buf {
* retention (after crash) only when ETR_MODE_RESRV buffer
* mode is enabled. Used by ETF for trace data retention
* (after crash) by default.
+ * @crash_mdata: Reserved memory for storing tmc crash metadata.
+ * Used by ETR/ETF.
*/
struct tmc_drvdata {
void __iomem *base;
@@ -228,6 +249,7 @@ struct tmc_drvdata {
struct etr_buf *sysfs_buf;
struct etr_buf *perf_buf;
struct tmc_resrv_buf crash_tbuf;
+ struct tmc_resrv_buf crash_mdata;
};
struct etr_buf_operations {
@@ -350,11 +372,32 @@ static inline bool is_tmc_reserved_region_valid(struct device *dev)
struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
if (drvdata->crash_tbuf.paddr &&
- drvdata->crash_tbuf.size)
+ drvdata->crash_tbuf.size &&
+ drvdata->crash_mdata.paddr &&
+ drvdata->crash_mdata.size)
return true;
return false;
}
+static inline uint32_t find_crash_metadata_crc(struct tmc_crash_metadata *md)
+{
+ unsigned long crc_size;
+
+ crc_size = sizeof(struct tmc_crash_metadata) -
+ offsetof(struct tmc_crash_metadata, crc32_tdata);
+ return crc32_le(0, (void *)&md->crc32_tdata, crc_size);
+}
+
+static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata,
+ struct tmc_crash_metadata *md)
+{
+ unsigned long crc_size;
+
+ /* Take CRC of configured buffer size to keep it simple */
+ crc_size = md->size << 2;
+ return crc32_le(0, (void *)drvdata->crash_tbuf.vaddr, crc_size);
+}
+
struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 5/7] coresight: tmc: Add support for reading crash data
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
` (3 preceding siblings ...)
2024-05-31 4:27 ` [PATCH v8 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:03 ` James Clark
2024-05-31 4:27 ` [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
2024-05-31 4:27 ` [PATCH v8 7/7] coresight: config: Add preloaded configuration Linu Cherian
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian, Anil Kumar Reddy, Tanmay Jagdale
* Introduce a new mode CS_MODE_READ_CRASHDATA for reading trace
captured in previous crash/watchdog reset.
* Add special device files for reading ETR/ETF crash data.
* User can read the crash data as below
For example, for reading crash data from tmc_etf sink
#dd if=/dev/crash_tmc_etfXX of=~/cstrace.bin
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
Changelog from v7:
* Moved crash dev registration into new function,
register_crash_dev_interface
* Removed redundant variable trace_addr in
tmc_etr_setup_crashdata_buf
.../coresight/coresight-etm4x-core.c | 1 +
.../hwtracing/coresight/coresight-tmc-core.c | 148 ++++++++++++++++-
.../hwtracing/coresight/coresight-tmc-etf.c | 73 +++++++++
.../hwtracing/coresight/coresight-tmc-etr.c | 152 +++++++++++++++++-
drivers/hwtracing/coresight/coresight-tmc.h | 11 +-
include/linux/coresight.h | 13 ++
6 files changed, 391 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index c2ca4a02dfce..5eb411e39b01 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1011,6 +1011,7 @@ static void etm4_disable(struct coresight_device *csdev,
switch (mode) {
case CS_MODE_DISABLED:
+ case CS_MODE_READ_CRASHDATA:
break;
case CS_MODE_SYSFS:
etm4_disable_sysfs(csdev);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 7170416c3e1a..aaa9de9f4cd2 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -103,6 +103,60 @@ u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
return mask;
}
+int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata)
+{
+ int ret = 0;
+ struct tmc_crash_metadata *mdata;
+ struct coresight_device *csdev = drvdata->csdev;
+
+ if (!drvdata->crash_mdata.vaddr) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ mdata = drvdata->crash_mdata.vaddr;
+ /* Check data integrity of metadata */
+ if (mdata->crc32_mdata != find_crash_metadata_crc(mdata)) {
+ dev_dbg(&drvdata->csdev->dev,
+ "CRC mismatch in tmc crash metadata\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ /* Check data integrity of tracedata */
+ if (mdata->crc32_tdata != find_crash_tracedata_crc(drvdata, mdata)) {
+ dev_dbg(&drvdata->csdev->dev,
+ "CRC mismatch in tmc crash tracedata\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ /* Check for valid metadata */
+ if (!mdata->valid) {
+ dev_dbg(&drvdata->csdev->dev,
+ "Data invalid in tmc crash metadata\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Sink specific crashdata mode preparation */
+ ret = crashdata_ops(csdev)->prepare(csdev);
+ if (ret)
+ goto out;
+
+ if (mdata->sts & 0x1)
+ coresight_insert_barrier_packet(drvdata->buf);
+
+out:
+ return ret;
+}
+
+int tmc_read_unprepare_crashdata(struct tmc_drvdata *drvdata)
+{
+ struct coresight_device *csdev = drvdata->csdev;
+
+ /* Sink specific crashdata mode preparation */
+ return crashdata_ops(csdev)->unprepare(csdev);
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
@@ -153,6 +207,9 @@ static int tmc_open(struct inode *inode, struct file *file)
struct tmc_drvdata *drvdata = container_of(file->private_data,
struct tmc_drvdata, miscdev);
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA)
+ return -EBUSY;
+
ret = tmc_read_prepare(drvdata);
if (ret)
return ret;
@@ -177,13 +234,12 @@ static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata,
return -EINVAL;
}
-static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
- loff_t *ppos)
+static ssize_t tmc_read_common(struct tmc_drvdata *drvdata, char __user *data,
+ size_t len, loff_t *ppos)
{
char *bufp;
ssize_t actual;
- struct tmc_drvdata *drvdata = container_of(file->private_data,
- struct tmc_drvdata, miscdev);
+
actual = tmc_get_sysfs_trace(drvdata, *ppos, len, &bufp);
if (actual <= 0)
return 0;
@@ -200,6 +256,16 @@ static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
return actual;
}
+static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
+ loff_t *ppos)
+{
+ struct tmc_drvdata *drvdata = container_of(file->private_data,
+ struct tmc_drvdata, miscdev);
+
+ return tmc_read_common(drvdata, data, len, ppos);
+}
+
+
static int tmc_release(struct inode *inode, struct file *file)
{
int ret;
@@ -222,6 +288,61 @@ static const struct file_operations tmc_fops = {
.llseek = no_llseek,
};
+static int tmc_crashdata_open(struct inode *inode, struct file *file)
+{
+ int ret;
+ struct tmc_drvdata *drvdata = container_of(file->private_data,
+ struct tmc_drvdata,
+ crashdev);
+
+ if (!coresight_take_mode(drvdata->csdev, CS_MODE_READ_CRASHDATA))
+ return -EBUSY;
+
+ ret = tmc_read_prepare(drvdata);
+ if (ret) {
+ coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
+ return ret;
+ }
+
+ nonseekable_open(inode, file);
+
+ dev_dbg(&drvdata->csdev->dev, "%s: successfully opened\n", __func__);
+ return 0;
+}
+
+static ssize_t tmc_crashdata_read(struct file *file, char __user *data,
+ size_t len, loff_t *ppos)
+{
+ struct tmc_drvdata *drvdata = container_of(file->private_data,
+ struct tmc_drvdata,
+ crashdev);
+
+ return tmc_read_common(drvdata, data, len, ppos);
+}
+
+static int tmc_crashdata_release(struct inode *inode, struct file *file)
+{
+ int ret = 0;
+ struct tmc_drvdata *drvdata = container_of(file->private_data,
+ struct tmc_drvdata,
+ crashdev);
+
+ ret = tmc_read_unprepare(drvdata);
+
+ coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED);
+
+ dev_dbg(&drvdata->csdev->dev, "%s: released\n", __func__);
+ return ret;
+}
+
+static const struct file_operations tmc_crashdata_fops = {
+ .owner = THIS_MODULE,
+ .open = tmc_crashdata_open,
+ .read = tmc_crashdata_read,
+ .release = tmc_crashdata_release,
+ .llseek = no_llseek,
+};
+
static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
{
enum tmc_mem_intf_width memwidth;
@@ -507,6 +628,18 @@ static u32 tmc_etr_get_max_burst_size(struct device *dev)
return burst_size;
}
+static void register_crash_dev_interface(struct tmc_drvdata * drvdata,
+ const char *name)
+{
+ drvdata->crashdev.name =
+ devm_kasprintf(&drvdata->csdev->dev, GFP_KERNEL, "%s_%s", "crash", name);
+ drvdata->crashdev.minor = MISC_DYNAMIC_MINOR;
+ drvdata->crashdev.fops = &tmc_crashdata_fops;
+ if (misc_register(&drvdata->crashdev))
+ dev_dbg(&drvdata->csdev->dev,
+ "Failed to setup user interface for crashdata\n");
+}
+
static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
{
int ret = 0;
@@ -619,6 +752,10 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
coresight_unregister(drvdata->csdev);
else
pm_runtime_put(&adev->dev);
+
+ if (is_tmc_reserved_region_valid(dev))
+ register_crash_dev_interface(drvdata, desc.name);
+
out:
return ret;
}
@@ -630,7 +767,8 @@ static void tmc_shutdown(struct amba_device *adev)
spin_lock_irqsave(&drvdata->spinlock, flags);
- if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED)
+ if ((coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) ||
+ (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA))
goto out;
if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index f9569585e9f8..655c0c0ba54b 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -657,6 +657,56 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev)
return 0;
}
+static int tmc_etb_setup_crashdata_buf(struct tmc_drvdata *drvdata)
+{
+ unsigned long size;
+ struct tmc_crash_metadata *mdata;
+ struct device *dev = &drvdata->csdev->dev;
+
+ mdata = drvdata->crash_mdata.vaddr;
+ size = mdata->size << 2;
+
+ /*
+ * Buffer address given by metadata for retrieval of trace data
+ * from previous boot is expected to be same as the reserved
+ * trace buffer memory region provided through DTS
+ */
+ if (is_tmc_reserved_region_valid(dev->parent)
+ && (drvdata->crash_tbuf.paddr == mdata->trc_paddr))
+ drvdata->buf = drvdata->crash_tbuf.vaddr;
+ else {
+ dev_dbg(dev, "Trace buffer address of previous boot invalid\n");
+ return -EINVAL;
+ }
+
+ drvdata->len = size;
+ return 0;
+}
+
+static void tmc_etb_free_crashdata_buf(struct tmc_drvdata *drvdata)
+{
+ void *buf = drvdata->buf;
+
+ if (!buf)
+ return;
+ drvdata->buf = NULL;
+}
+
+static int tmc_etb_prepare_crashdata(struct coresight_device *csdev)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ return tmc_etb_setup_crashdata_buf(drvdata);
+}
+
+static int tmc_etb_unprepare_crashdata(struct coresight_device *csdev)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ tmc_etb_free_crashdata_buf(drvdata);
+ return 0;
+}
+
static const struct coresight_ops_sink tmc_etf_sink_ops = {
.enable = tmc_enable_etf_sink,
.disable = tmc_disable_etf_sink,
@@ -674,6 +724,11 @@ static const struct coresight_ops_panic tmc_etf_sync_ops = {
.sync = tmc_panic_sync_etf,
};
+static const struct coresight_ops_crashdata tmc_etf_crashdata_ops = {
+ .prepare = tmc_etb_prepare_crashdata,
+ .unprepare = tmc_etb_unprepare_crashdata,
+};
+
const struct coresight_ops tmc_etb_cs_ops = {
.sink_ops = &tmc_etf_sink_ops,
};
@@ -682,6 +737,7 @@ const struct coresight_ops tmc_etf_cs_ops = {
.sink_ops = &tmc_etf_sink_ops,
.link_ops = &tmc_etf_link_ops,
.panic_ops = &tmc_etf_sync_ops,
+ .crashdata_ops = &tmc_etf_crashdata_ops,
};
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
@@ -702,6 +758,14 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
goto out;
}
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA) {
+ ret = tmc_read_prepare_crashdata(drvdata);
+ if (ret)
+ goto out;
+ else
+ goto mode_valid;
+ }
+
/* Don't interfere if operated from Perf */
if (coresight_get_mode(drvdata->csdev) == CS_MODE_PERF) {
ret = -EINVAL;
@@ -725,6 +789,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
__tmc_etb_disable_hw(drvdata);
}
+mode_valid:
drvdata->reading = true;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -744,8 +809,16 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
drvdata->config_type != TMC_CONFIG_TYPE_ETF))
return -EINVAL;
+
spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA) {
+ tmc_read_unprepare_crashdata(drvdata);
+ drvdata->reading = false;
+ spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ return 0;
+ }
+
/* Re-enable the TMC if need be */
if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) {
/* There is no point in reading a TMC in HW FIFO mode */
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index be1079e8fd64..74f53972ce3c 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1160,7 +1160,12 @@ ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
{
s64 offset;
ssize_t actual = len;
- struct etr_buf *etr_buf = drvdata->sysfs_buf;
+ struct etr_buf *etr_buf;
+
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA)
+ etr_buf = drvdata->sysfs_crash_buf;
+ else
+ etr_buf = drvdata->sysfs_buf;
if (pos + actual > etr_buf->len)
actual = etr_buf->len - pos;
@@ -1878,6 +1883,128 @@ static int tmc_panic_sync_etr(struct coresight_device *csdev)
return 0;
}
+static int tmc_etr_setup_crashdata_buf(struct tmc_drvdata *drvdata)
+{
+ int rc = 0;
+ struct etr_buf *etr_buf;
+ struct etr_flat_buf *resrv_buf;
+ struct tmc_crash_metadata *mdata;
+ struct device *dev = &drvdata->csdev->dev;
+
+ mdata = drvdata->crash_mdata.vaddr;
+
+ etr_buf = kzalloc(sizeof(*etr_buf), GFP_ATOMIC);
+ if (!etr_buf) {
+ rc = -ENOMEM;
+ goto out;
+ }
+ etr_buf->size = drvdata->crash_tbuf.size;
+
+ resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_ATOMIC);
+ if (!resrv_buf) {
+ rc = -ENOMEM;
+ goto rmem_err;
+ }
+
+ /*
+ * Buffer address given by metadata for retrieval of trace data
+ * from previous boot is expected to be same as the reserved
+ * trace buffer memory region provided through DTS
+ */
+ if (is_tmc_reserved_region_valid(dev->parent)
+ && (drvdata->crash_tbuf.paddr == mdata->trc_paddr))
+ resrv_buf->vaddr = drvdata->crash_tbuf.vaddr;
+ else {
+ dev_dbg(dev, "Trace buffer address of previous boot invalid\n");
+ rc = -EINVAL;
+ goto map_err;
+ }
+
+ resrv_buf->size = etr_buf->size;
+ resrv_buf->dev = &drvdata->csdev->dev;
+ etr_buf->mode = ETR_MODE_RESRV;
+ etr_buf->private = resrv_buf;
+ etr_buf->ops = etr_buf_ops[ETR_MODE_RESRV];
+
+ drvdata->sysfs_crash_buf = etr_buf;
+
+ return 0;
+
+map_err:
+ kfree(resrv_buf);
+
+rmem_err:
+ kfree(etr_buf);
+
+out:
+ return rc;
+}
+
+static int tmc_etr_sync_crashdata_buf(struct tmc_drvdata *drvdata)
+{
+ u32 status;
+ u64 rrp, rwp, dba;
+ struct tmc_crash_metadata *mdata;
+ struct etr_buf *etr_buf = drvdata->sysfs_crash_buf;
+
+ mdata = drvdata->crash_mdata.vaddr;
+
+ rrp = mdata->rrp;
+ rwp = mdata->rwp;
+ dba = mdata->dba;
+ status = mdata->sts;
+
+ etr_buf->full = !!(status & TMC_STS_FULL);
+
+ /* Sync the buffer pointers */
+ etr_buf->offset = rrp - dba;
+ if (etr_buf->full)
+ etr_buf->len = etr_buf->size;
+ else
+ etr_buf->len = rwp - rrp;
+
+ /* Additional sanity checks for validating metadata */
+ if ((etr_buf->offset > etr_buf->size) ||
+ (etr_buf->len > etr_buf->size)) {
+ dev_dbg(&drvdata->csdev->dev,
+ "Offset and length invalid in tmc crash metadata\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void tmc_etr_free_crashdata_buf(struct tmc_drvdata *drvdata)
+{
+ struct etr_buf *etr_buf = drvdata->sysfs_crash_buf;
+
+ if (!etr_buf)
+ return;
+ drvdata->sysfs_crash_buf = NULL;
+}
+
+static int tmc_etr_prepare_crashdata(struct coresight_device *csdev)
+{
+ int ret = 0;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ ret = tmc_etr_setup_crashdata_buf(drvdata);
+ if (ret)
+ goto out;
+ ret = tmc_etr_sync_crashdata_buf(drvdata);
+
+out:
+ return ret;
+}
+
+static int tmc_etr_unprepare_crashdata(struct coresight_device *csdev)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ tmc_etr_free_crashdata_buf(drvdata);
+ return 0;
+}
+
static const struct coresight_ops_sink tmc_etr_sink_ops = {
.enable = tmc_enable_etr_sink,
.disable = tmc_disable_etr_sink,
@@ -1890,9 +2017,15 @@ static const struct coresight_ops_panic tmc_etr_sync_ops = {
.sync = tmc_panic_sync_etr,
};
+static const struct coresight_ops_crashdata tmc_etr_crashdata_ops = {
+ .prepare = tmc_etr_prepare_crashdata,
+ .unprepare = tmc_etr_unprepare_crashdata,
+};
+
const struct coresight_ops tmc_etr_cs_ops = {
.sink_ops = &tmc_etr_sink_ops,
.panic_ops = &tmc_etr_sync_ops,
+ .crashdata_ops = &tmc_etr_crashdata_ops,
};
int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
@@ -1904,12 +2037,21 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
return -EINVAL;
+
spin_lock_irqsave(&drvdata->spinlock, flags);
if (drvdata->reading) {
ret = -EBUSY;
goto out;
}
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA) {
+ ret = tmc_read_prepare_crashdata(drvdata);
+ if (ret)
+ goto out;
+ else
+ goto mode_valid;
+ }
+
/*
* We can safely allow reads even if the ETR is operating in PERF mode,
* since the sysfs session is captured in mode specific data.
@@ -1924,6 +2066,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS)
__tmc_etr_disable_hw(drvdata);
+mode_valid:
drvdata->reading = true;
out:
spin_unlock_irqrestore(&drvdata->spinlock, flags);
@@ -1942,6 +2085,12 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
spin_lock_irqsave(&drvdata->spinlock, flags);
+ if (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA) {
+ sysfs_buf = drvdata->sysfs_crash_buf;
+ tmc_read_unprepare_crashdata(drvdata);
+ goto out;
+ }
+
/* RE-enable the TMC if need be */
if (coresight_get_mode(drvdata->csdev) == CS_MODE_SYSFS) {
/*
@@ -1959,6 +2108,7 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
drvdata->sysfs_buf = NULL;
}
+out:
drvdata->reading = false;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 875d4129da7c..528174283ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -200,6 +200,8 @@ struct tmc_resrv_buf {
* @base: memory mapped base address for this component.
* @csdev: component vitals needed by the framework.
* @miscdev: specifics to handle "/dev/xyz.tmc" entry.
+ * @crashdev: specifics to handle "/dev/crash_tmc_xyz" entry for reading
+ * crash tracedata.
* @spinlock: only one at a time pls.
* @pid: Process ID of the process being monitored by the session
* that is using this component.
@@ -218,7 +220,10 @@ struct tmc_resrv_buf {
* @idr_mutex: Access serialisation for idr.
* @sysfs_buf: SYSFS buffer for ETR.
* @perf_buf: PERF buffer for ETR.
- * @crash_tbuf: Used by ETR as hardware trace buffer and for trace data
+ * @sysfs_crash_buf: Sysfs crashdata buffer for ETR. This is a special purpose
+ * buffer that is used only for mapping the trace buffer from
+ * previous crash and not for capturing trace.
+ * @crash_tbuf: Used by ETR as hardware trace buffer and for trace data
* retention (after crash) only when ETR_MODE_RESRV buffer
* mode is enabled. Used by ETF for trace data retention
* (after crash) by default.
@@ -229,6 +234,7 @@ struct tmc_drvdata {
void __iomem *base;
struct coresight_device *csdev;
struct miscdevice miscdev;
+ struct miscdevice crashdev;
spinlock_t spinlock;
pid_t pid;
bool reading;
@@ -248,6 +254,7 @@ struct tmc_drvdata {
struct mutex idr_mutex;
struct etr_buf *sysfs_buf;
struct etr_buf *perf_buf;
+ struct etr_buf *sysfs_crash_buf;
struct tmc_resrv_buf crash_tbuf;
struct tmc_resrv_buf crash_mdata;
};
@@ -299,6 +306,8 @@ void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
+int tmc_read_prepare_crashdata(struct tmc_drvdata *drvdata);
+int tmc_read_unprepare_crashdata(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index b156467c9baa..b5e825b25e9d 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -308,6 +308,7 @@ enum cs_mode {
CS_MODE_DISABLED,
CS_MODE_SYSFS,
CS_MODE_PERF,
+ CS_MODE_READ_CRASHDATA, /* Trace data from previous crash */
};
#define source_ops(csdev) csdev->ops->source_ops
@@ -316,6 +317,7 @@ enum cs_mode {
#define helper_ops(csdev) csdev->ops->helper_ops
#define ect_ops(csdev) csdev->ops->ect_ops
#define panic_ops(csdev) csdev->ops->panic_ops
+#define crashdata_ops(csdev) csdev->ops->crashdata_ops
/**
* struct coresight_ops_sink - basic operations for a sink
@@ -395,12 +397,23 @@ struct coresight_ops_panic {
int (*sync)(struct coresight_device *csdev);
};
+/**
+ * struct coresight_ops_crashdata - Generic device ops for crashdata mode
+ *
+ * @prepare : Preparation for reading crashdata mode
+ */
+struct coresight_ops_crashdata {
+ int (*prepare)(struct coresight_device *csdev);
+ int (*unprepare)(struct coresight_device *csdev);
+};
+
struct coresight_ops {
const struct coresight_ops_sink *sink_ops;
const struct coresight_ops_link *link_ops;
const struct coresight_ops_source *source_ops;
const struct coresight_ops_helper *helper_ops;
const struct coresight_ops_panic *panic_ops;
+ const struct coresight_ops_crashdata *crashdata_ops;
};
static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
` (4 preceding siblings ...)
2024-05-31 4:27 ` [PATCH v8 5/7] coresight: tmc: Add support for reading crash data Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:16 ` James Clark
2024-05-31 4:27 ` [PATCH v8 7/7] coresight: config: Add preloaded configuration Linu Cherian
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian
Configure TMC ETR and ETF to flush and stop trace capture
on FlIn event based on sysfs attribute,
/sys/bus/coresight/devices/tmc_etXn/stop_on_flush.
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
Changelog from v7:
* Honour stop_on_flush sysfs attribute for perf sessions as well.
This allows user to start trace sessions using perf method as
well to use the Coresight kernel panic support.
.../hwtracing/coresight/coresight-tmc-core.c | 31 +++++++++++++++++++
.../hwtracing/coresight/coresight-tmc-etf.c | 18 ++++++++---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++---
drivers/hwtracing/coresight/coresight-tmc.h | 4 +++
4 files changed, 61 insertions(+), 10 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index aaa9de9f4cd2..24edd9d750c3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -452,9 +452,40 @@ static ssize_t buffer_size_store(struct device *dev,
static DEVICE_ATTR_RW(buffer_size);
+static ssize_t stop_on_flush_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ return sprintf(buf, "%#x\n", drvdata->stop_on_flush);
+}
+
+static ssize_t stop_on_flush_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t size)
+{
+ int ret;
+ u8 val;
+ struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ ret = kstrtou8(buf, 0, &val);
+ if (ret)
+ return ret;
+ if (val)
+ drvdata->stop_on_flush = true;
+ else
+ drvdata->stop_on_flush = false;
+
+ return size;
+}
+
+static DEVICE_ATTR_RW(stop_on_flush);
+
+
static struct attribute *coresight_tmc_attrs[] = {
&dev_attr_trigger_cntr.attr,
&dev_attr_buffer_size.attr,
+ &dev_attr_stop_on_flush.attr,
NULL,
};
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 655c0c0ba54b..1529b9cc210a 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -19,6 +19,7 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev,
static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
{
int rc = 0;
+ u32 ffcr;
CS_UNLOCK(drvdata->base);
@@ -32,10 +33,12 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
}
writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
- writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
- TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
- TMC_FFCR_TRIGON_TRIGIN,
- drvdata->base + TMC_FFCR);
+
+ ffcr = TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN |
+ TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN;
+ if (drvdata->stop_on_flush_en)
+ ffcr |= TMC_FFCR_STOP_ON_FLUSH;
+ writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
tmc_enable_hw(drvdata);
@@ -225,7 +228,8 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev)
used = true;
drvdata->buf = buf;
}
-
+ if (drvdata->stop_on_flush)
+ drvdata->stop_on_flush_en = true;
ret = tmc_etb_enable_hw(drvdata);
if (!ret) {
coresight_set_mode(csdev, CS_MODE_SYSFS);
@@ -288,6 +292,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data)
break;
}
+ if (drvdata->stop_on_flush)
+ drvdata->stop_on_flush_en = true;
ret = tmc_etb_enable_hw(drvdata);
if (!ret) {
/* Associate with monitored process. */
@@ -349,6 +355,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev)
tmc_etb_disable_hw(drvdata);
/* Dissociate from monitored process. */
drvdata->pid = -1;
+ /* Reset stop on flush */
+ drvdata->stop_on_flush_en = false;
coresight_set_mode(csdev, CS_MODE_DISABLED);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 74f53972ce3c..bf2d0932e205 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1059,7 +1059,7 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
{
- u32 axictl, sts;
+ u32 axictl, sts, ffcr;
struct etr_buf *etr_buf = drvdata->etr_buf;
int rc = 0;
@@ -1105,10 +1105,12 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(sts, drvdata->base + TMC_STS);
}
- writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
- TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
- TMC_FFCR_TRIGON_TRIGIN,
- drvdata->base + TMC_FFCR);
+ ffcr = TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN |
+ TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN;
+ if (drvdata->stop_on_flush_en)
+ ffcr |= TMC_FFCR_STOP_ON_FLUSH;
+ writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
+
writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
tmc_enable_hw(drvdata);
@@ -1313,6 +1315,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
goto out;
}
+ if (drvdata->stop_on_flush)
+ drvdata->stop_on_flush_en = true;
ret = tmc_etr_enable_hw(drvdata, sysfs_buf);
if (!ret) {
coresight_set_mode(csdev, CS_MODE_SYSFS);
@@ -1758,6 +1762,8 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
goto unlock_out;
}
+ if (drvdata->stop_on_flush)
+ drvdata->stop_on_flush_en = true;
rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
if (!rc) {
/* Associate with monitored process. */
@@ -1808,6 +1814,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
tmc_etr_disable_hw(drvdata);
/* Dissociate from monitored process. */
drvdata->pid = -1;
+ /* Reset stop on flush */
+ drvdata->stop_on_flush_en = false;
coresight_set_mode(csdev, CS_MODE_DISABLED);
/* Reset perf specific data */
drvdata->perf_buf = NULL;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 528174283ecc..81eadb384b83 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -205,6 +205,8 @@ struct tmc_resrv_buf {
* @spinlock: only one at a time pls.
* @pid: Process ID of the process being monitored by the session
* that is using this component.
+ * @stop_on_flush: Stop on flush trigger user configuration.
+ * @stop_on_flush_en: Stop on flush enable flag
* @buf: Snapshot of the trace data for ETF/ETB.
* @etr_buf: details of buffer used in TMC-ETR
* @len: size of the available trace for ETF/ETB.
@@ -238,6 +240,8 @@ struct tmc_drvdata {
spinlock_t spinlock;
pid_t pid;
bool reading;
+ bool stop_on_flush;
+ bool stop_on_flush_en;
union {
char *buf; /* TMC ETB */
struct etr_buf *etr_buf; /* TMC ETR */
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v8 7/7] coresight: config: Add preloaded configuration
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
` (5 preceding siblings ...)
2024-05-31 4:27 ` [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
@ 2024-05-31 4:27 ` Linu Cherian
2024-05-31 10:19 ` James Clark
6 siblings, 1 reply; 16+ messages in thread
From: Linu Cherian @ 2024-05-31 4:27 UTC (permalink / raw)
To: suzuki.poulose, mike.leach, james.clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Linu Cherian
Add a preloaded configuration for generating
external trigger on address match. This can be
used by CTI and ETR blocks to stop trace capture
on kernel panic.
Kernel address for "panic" function is used as the
default trigger address.
This new configuration is available as,
/sys/kernel/config/cs-syscfg/configurations/panicstop
Signed-off-by: Linu Cherian <lcherian@marvell.com>
---
drivers/hwtracing/coresight/Makefile | 2 +-
.../coresight/coresight-cfg-preload.c | 2 +
.../coresight/coresight-cfg-preload.h | 2 +
.../hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++++++++++++++++
4 files changed, 88 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 4ba478211b31..46ce7f39d05f 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -25,7 +25,7 @@ subdir-ccflags-y += $(condflags)
obj-$(CONFIG_CORESIGHT) += coresight.o
coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
coresight-sysfs.o coresight-syscfg.o coresight-config.o \
- coresight-cfg-preload.o coresight-cfg-afdo.o \
+ coresight-cfg-preload.o coresight-cfg-afdo.o coresight-cfg-pstop.o \
coresight-syscfg-configfs.o coresight-trace-id.o
obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/hwtracing/coresight/coresight-cfg-preload.c
index e237a4edfa09..4980e68483c5 100644
--- a/drivers/hwtracing/coresight/coresight-cfg-preload.c
+++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c
@@ -13,6 +13,7 @@
static struct cscfg_feature_desc *preload_feats[] = {
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
&strobe_etm4x,
+ &gen_etrig_etm4x,
#endif
NULL
};
@@ -20,6 +21,7 @@ static struct cscfg_feature_desc *preload_feats[] = {
static struct cscfg_config_desc *preload_cfgs[] = {
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
&afdo_etm4x,
+ &pstop_etm4x,
#endif
NULL
};
diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/hwtracing/coresight/coresight-cfg-preload.h
index 21299e175477..291ba530a6a5 100644
--- a/drivers/hwtracing/coresight/coresight-cfg-preload.h
+++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h
@@ -10,4 +10,6 @@
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
extern struct cscfg_feature_desc strobe_etm4x;
extern struct cscfg_config_desc afdo_etm4x;
+extern struct cscfg_feature_desc gen_etrig_etm4x;
+extern struct cscfg_config_desc pstop_etm4x;
#endif
diff --git a/drivers/hwtracing/coresight/coresight-cfg-pstop.c b/drivers/hwtracing/coresight/coresight-cfg-pstop.c
new file mode 100644
index 000000000000..c2bfbd07bfaf
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cfg-pstop.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright(C) 2023 Marvell.
+ * Based on coresight-cfg-afdo.c
+ */
+
+#include "coresight-config.h"
+
+/* ETMv4 includes and features */
+#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
+#include "coresight-etm4x-cfg.h"
+
+/* preload configurations and features */
+
+/* preload in features for ETMv4 */
+
+/* panic_stop feature */
+static struct cscfg_parameter_desc gen_etrig_params[] = {
+ {
+ .name = "address",
+ .value = (u64)panic,
+ },
+};
+
+static struct cscfg_regval_desc gen_etrig_regs[] = {
+ /* resource selector */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCRSCTLRn(2),
+ .hw_info = ETM4_CFG_RES_SEL,
+ .val32 = 0x40001,
+ },
+ /* single address comparator */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_64BIT |
+ CS_CFG_REG_TYPE_VAL_PARAM,
+ .offset = TRCACVRn(0),
+ .val32 = 0x0,
+ },
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCACATRn(0),
+ .val64 = 0xf00,
+ },
+ /* Driver external output[0] with comparator out */
+ {
+ .type = CS_CFG_REG_TYPE_RESOURCE,
+ .offset = TRCEVENTCTL0R,
+ .val32 = 0x2,
+ },
+ /* end of regs */
+};
+
+struct cscfg_feature_desc gen_etrig_etm4x = {
+ .name = "gen_etrig",
+ .description = "Generate external trigger on address match\n"
+ "parameter \'address\': address of kernel address\n",
+ .match_flags = CS_CFG_MATCH_CLASS_SRC_ETM4,
+ .nr_params = ARRAY_SIZE(gen_etrig_params),
+ .params_desc = gen_etrig_params,
+ .nr_regs = ARRAY_SIZE(gen_etrig_regs),
+ .regs_desc = gen_etrig_regs,
+};
+
+/* create a panic stop configuration */
+
+/* the total number of parameters in used features */
+#define PSTOP_NR_PARAMS ARRAY_SIZE(gen_etrig_params)
+
+static const char *pstop_ref_names[] = {
+ "gen_etrig",
+};
+
+struct cscfg_config_desc pstop_etm4x = {
+ .name = "panicstop",
+ .description = "Stop ETM on kernel panic\n",
+ .nr_feat_refs = ARRAY_SIZE(pstop_ref_names),
+ .feat_ref_names = pstop_ref_names,
+ .nr_total_params = PSTOP_NR_PARAMS,
+};
+
+/* end of ETM4x configurations */
+#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */
--
2.34.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 5/7] coresight: tmc: Add support for reading crash data
2024-05-31 4:27 ` [PATCH v8 5/7] coresight: tmc: Add support for reading crash data Linu Cherian
@ 2024-05-31 10:03 ` James Clark
2024-06-05 4:46 ` [EXTERNAL] " Linu Cherian
0 siblings, 1 reply; 16+ messages in thread
From: James Clark @ 2024-05-31 10:03 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Anil Kumar Reddy, Tanmay Jagdale, suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> * Introduce a new mode CS_MODE_READ_CRASHDATA for reading trace
> captured in previous crash/watchdog reset.
>
> * Add special device files for reading ETR/ETF crash data.
>
> * User can read the crash data as below
>
> For example, for reading crash data from tmc_etf sink
>
> #dd if=/dev/crash_tmc_etfXX of=~/cstrace.bin
>
> Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
> Changelog from v7:
> * Moved crash dev registration into new function,
> register_crash_dev_interface
> * Removed redundant variable trace_addr in
> tmc_etr_setup_crashdata_buf
>
> .../coresight/coresight-etm4x-core.c | 1 +
> .../hwtracing/coresight/coresight-tmc-core.c | 148 ++++++++++++++++-
> .../hwtracing/coresight/coresight-tmc-etf.c | 73 +++++++++
> .../hwtracing/coresight/coresight-tmc-etr.c | 152 +++++++++++++++++-
> drivers/hwtracing/coresight/coresight-tmc.h | 11 +-
> include/linux/coresight.h | 13 ++
> 6 files changed, 391 insertions(+), 7 deletions(-)
>
[...]
> +static void register_crash_dev_interface(struct tmc_drvdata * drvdata,
> + const char *name)
> +{
> + drvdata->crashdev.name =
> + devm_kasprintf(&drvdata->csdev->dev, GFP_KERNEL, "%s_%s", "crash", name);
> + drvdata->crashdev.minor = MISC_DYNAMIC_MINOR;
> + drvdata->crashdev.fops = &tmc_crashdata_fops;
> + if (misc_register(&drvdata->crashdev))
> + dev_dbg(&drvdata->csdev->dev,
> + "Failed to setup user interface for crashdata\n");
> +}
> +
> static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> {
> int ret = 0;
> @@ -619,6 +752,10 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> coresight_unregister(drvdata->csdev);
> else
> pm_runtime_put(&adev->dev);
> +
> + if (is_tmc_reserved_region_valid(dev))
> + register_crash_dev_interface(drvdata, desc.name);
> +
Now that you've added an extra step to the probe you need to add a "goto
out" when the previous step fails:
if (ret) {
coresight_unregister(drvdata->csdev);
+ goto out;
}
That seems to be the pattern in the rest of the function. Otherwise you
might register the interface on no device.
There's also a conflict here and in some other places. Since this has to
go through the coresight branch you should base it off of coresight-next.
> out:
> return ret;
> }
> @@ -630,7 +767,8 @@ static void tmc_shutdown(struct amba_device *adev)
>
> spin_lock_irqsave(&drvdata->spinlock, flags);
>
> - if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED)
> + if ((coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED) ||
> + (coresight_get_mode(drvdata->csdev) == CS_MODE_READ_CRASHDATA))
> goto out;
>
> if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index f9569585e9f8..655c0c0ba54b 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -657,6 +657,56 @@ static int tmc_panic_sync_etf(struct coresight_device *csdev)
> return 0;
> }
>
[...]
> @@ -725,6 +789,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
> __tmc_etb_disable_hw(drvdata);
> }
>
> +mode_valid:
> drvdata->reading = true;
> out:
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> @@ -744,8 +809,16 @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
> drvdata->config_type != TMC_CONFIG_TYPE_ETF))
> return -EINVAL;
>
> +
Whitespace change. There are a couple of other minor checkpatch style
warnings.
The rest looks good to me. All the tests are passing. I still think we
should all the kself test for this mode, but that can be done later.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory
2024-05-31 4:27 ` [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
@ 2024-05-31 10:05 ` James Clark
0 siblings, 0 replies; 16+ messages in thread
From: James Clark @ 2024-05-31 10:05 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
Anil Kumar Reddy, suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> Add support to use reserved memory for coresight ETR trace buffer.
>
> Introduce a new ETR buffer mode called ETR_MODE_RESRV, which
> becomes available when ETR device tree node is supplied with a valid
> reserved memory region.
>
> ETR_MODE_RESRV can be selected only by explicit user request.
>
> $ echo resrv >/sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred
>
> Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
> Changelog from v7:
> * Reverted all changes in tmc_alloc_etr_buf that has creeped in by mistake
> during refactoring. This fixes the "perf test" breakage.
>
Reviewed-by: James Clark <james.clark@arm.com>
>
> .../hwtracing/coresight/coresight-tmc-core.c | 47 +++++++++++
> .../hwtracing/coresight/coresight-tmc-etr.c | 79 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tmc.h | 27 +++++++
> 3 files changed, 153 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index 72005b0c633e..1325387d6257 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -22,6 +22,7 @@
> #include <linux/spinlock.h>
> #include <linux/pm_runtime.h>
> #include <linux/of.h>
> +#include <linux/of_address.h>
> #include <linux/coresight.h>
> #include <linux/amba/bus.h>
>
> @@ -370,6 +371,50 @@ static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata)
> return (auth & TMC_AUTH_NSID_MASK) == 0x3;
> }
>
> +static struct device_node *tmc_get_region_byname(struct device_node *node,
> + char *name)
> +{
> + int index;
> +
> + index = of_property_match_string(node, "memory-region-names", name);
> + if (index < 0)
> + return ERR_PTR(-ENODEV);
> +
> + return of_parse_phandle(node, "memory-region", index);
> +}
> +
> +static void tmc_get_reserved_region(struct device *parent)
> +{
> + struct tmc_drvdata *drvdata = dev_get_drvdata(parent);
> + struct device_node *node;
> + struct resource res;
> + int rc;
> +
> + node = tmc_get_region_byname(parent->of_node, "tracedata");
> + if (IS_ERR_OR_NULL(node)) {
> + dev_dbg(parent, "No reserved trace buffer specified\n");
> + return;
> + }
> +
> + rc = of_address_to_resource(node, 0, &res);
> + of_node_put(node);
> + if (rc || res.start == 0 || resource_size(&res) == 0) {
> + dev_err(parent, "Reserved trace buffer memory is invalid\n");
> + return;
> + }
> +
> + drvdata->crash_tbuf.vaddr = memremap(res.start,
> + resource_size(&res),
> + MEMREMAP_WC);
> + if (IS_ERR_OR_NULL(drvdata->crash_tbuf.vaddr)) {
> + dev_err(parent, "Reserved trace buffer mapping failed\n");
> + return;
> + }
> +
> + drvdata->crash_tbuf.paddr = res.start;
> + drvdata->crash_tbuf.size = resource_size(&res);
> +}
> +
> /* Detect and initialise the capabilities of a TMC ETR */
> static int tmc_etr_setup_caps(struct device *parent, u32 devid, void *dev_caps)
> {
> @@ -482,6 +527,8 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
> }
>
> + tmc_get_reserved_region(dev);
> +
> desc.dev = dev;
>
> switch (drvdata->config_type) {
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index e75428fa1592..041c428dd7cd 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -30,6 +30,7 @@ struct etr_buf_hw {
> bool has_iommu;
> bool has_etr_sg;
> bool has_catu;
> + bool has_resrv;
> };
>
> /*
> @@ -694,6 +695,75 @@ static const struct etr_buf_operations etr_flat_buf_ops = {
> .get_data = tmc_etr_get_data_flat_buf,
> };
>
> +/*
> + * tmc_etr_alloc_resrv_buf: Allocate a contiguous DMA buffer from reserved region.
> + */
> +static int tmc_etr_alloc_resrv_buf(struct tmc_drvdata *drvdata,
> + struct etr_buf *etr_buf, int node,
> + void **pages)
> +{
> + struct etr_flat_buf *resrv_buf;
> + struct device *real_dev = drvdata->csdev->dev.parent;
> +
> + /* We cannot reuse existing pages for resrv buf */
> + if (pages)
> + return -EINVAL;
> +
> + resrv_buf = kzalloc(sizeof(*resrv_buf), GFP_KERNEL);
> + if (!resrv_buf)
> + return -ENOMEM;
> +
> + resrv_buf->daddr = dma_map_resource(real_dev, drvdata->crash_tbuf.paddr,
> + drvdata->crash_tbuf.size,
> + DMA_FROM_DEVICE, 0);
> + if (dma_mapping_error(real_dev, resrv_buf->daddr)) {
> + dev_err(real_dev, "failed to map source buffer address\n");
> + kfree(resrv_buf);
> + return -ENOMEM;
> + }
> +
> + resrv_buf->vaddr = drvdata->crash_tbuf.vaddr;
> + resrv_buf->size = etr_buf->size = drvdata->crash_tbuf.size;
> + resrv_buf->dev = &drvdata->csdev->dev;
> + etr_buf->hwaddr = resrv_buf->daddr;
> + etr_buf->mode = ETR_MODE_RESRV;
> + etr_buf->private = resrv_buf;
> + return 0;
> +}
> +
> +static void tmc_etr_free_resrv_buf(struct etr_buf *etr_buf)
> +{
> + struct etr_flat_buf *resrv_buf = etr_buf->private;
> +
> + if (resrv_buf && resrv_buf->daddr) {
> + struct device *real_dev = resrv_buf->dev->parent;
> +
> + dma_unmap_resource(real_dev, resrv_buf->daddr,
> + resrv_buf->size, DMA_FROM_DEVICE, 0);
> + }
> + kfree(resrv_buf);
> +}
> +
> +static void tmc_etr_sync_resrv_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
> +{
> + /*
> + * Adjust the buffer to point to the beginning of the trace data
> + * and update the available trace data.
> + */
> + etr_buf->offset = rrp - etr_buf->hwaddr;
> + if (etr_buf->full)
> + etr_buf->len = etr_buf->size;
> + else
> + etr_buf->len = rwp - rrp;
> +}
> +
> +static const struct etr_buf_operations etr_resrv_buf_ops = {
> + .alloc = tmc_etr_alloc_resrv_buf,
> + .free = tmc_etr_free_resrv_buf,
> + .sync = tmc_etr_sync_resrv_buf,
> + .get_data = tmc_etr_get_data_flat_buf,
> +};
> +
> /*
> * tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters
> * appropriately.
> @@ -800,6 +870,7 @@ static const struct etr_buf_operations *etr_buf_ops[] = {
> [ETR_MODE_FLAT] = &etr_flat_buf_ops,
> [ETR_MODE_ETR_SG] = &etr_sg_buf_ops,
> [ETR_MODE_CATU] = NULL,
> + [ETR_MODE_RESRV] = &etr_resrv_buf_ops
> };
>
> void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu)
> @@ -825,6 +896,7 @@ static inline int tmc_etr_mode_alloc_buf(int mode,
> case ETR_MODE_FLAT:
> case ETR_MODE_ETR_SG:
> case ETR_MODE_CATU:
> + case ETR_MODE_RESRV:
> if (etr_buf_ops[mode] && etr_buf_ops[mode]->alloc)
> rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf,
> node, pages);
> @@ -843,6 +915,7 @@ static void get_etr_buf_hw(struct device *dev, struct etr_buf_hw *buf_hw)
> buf_hw->has_iommu = iommu_get_domain_for_dev(dev->parent);
> buf_hw->has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);
> buf_hw->has_catu = !!tmc_etr_get_catu_device(drvdata);
> + buf_hw->has_resrv = is_tmc_reserved_region_valid(dev->parent);
> }
>
> static bool etr_can_use_flat_mode(struct etr_buf_hw *buf_hw, ssize_t etr_buf_size)
> @@ -1830,6 +1903,7 @@ static const char *const buf_modes_str[] = {
> [ETR_MODE_FLAT] = "flat",
> [ETR_MODE_ETR_SG] = "tmc-sg",
> [ETR_MODE_CATU] = "catu",
> + [ETR_MODE_RESRV] = "resrv",
> [ETR_MODE_AUTO] = "auto",
> };
>
> @@ -1848,6 +1922,9 @@ static ssize_t buf_modes_available_show(struct device *dev,
> if (buf_hw.has_catu)
> size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_CATU]);
>
> + if (buf_hw.has_resrv)
> + size += sysfs_emit_at(buf, size, "%s ", buf_modes_str[ETR_MODE_RESRV]);
> +
> size += sysfs_emit_at(buf, size, "\n");
> return size;
> }
> @@ -1875,6 +1952,8 @@ static ssize_t buf_mode_preferred_store(struct device *dev,
> drvdata->etr_mode = ETR_MODE_ETR_SG;
> else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_CATU]) && buf_hw.has_catu)
> drvdata->etr_mode = ETR_MODE_CATU;
> + else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_RESRV]) && buf_hw.has_resrv)
> + drvdata->etr_mode = ETR_MODE_RESRV;
> else if (sysfs_streq(buf, buf_modes_str[ETR_MODE_AUTO]))
> drvdata->etr_mode = ETR_MODE_AUTO;
> else
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index cef979c897e6..2abc5387cdf7 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -135,6 +135,7 @@ enum etr_mode {
> ETR_MODE_FLAT, /* Uses contiguous flat buffer */
> ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
> ETR_MODE_CATU, /* Use SG mechanism in CATU */
> + ETR_MODE_RESRV, /* Use reserved region contiguous buffer */
> ETR_MODE_AUTO, /* Use the default mechanism */
> };
>
> @@ -164,6 +165,17 @@ struct etr_buf {
> void *private;
> };
>
> +/**
> + * @paddr : Start address of reserved memory region.
> + * @vaddr : Corresponding CPU virtual address.
> + * @size : Size of reserved memory region.
> + */
> +struct tmc_resrv_buf {
> + phys_addr_t paddr;
> + void *vaddr;
> + size_t size;
> +};
> +
> /**
> * struct tmc_drvdata - specifics associated to an TMC component
> * @base: memory mapped base address for this component.
> @@ -187,6 +199,10 @@ struct etr_buf {
> * @idr_mutex: Access serialisation for idr.
> * @sysfs_buf: SYSFS buffer for ETR.
> * @perf_buf: PERF buffer for ETR.
> + * @crash_tbuf: Used by ETR as hardware trace buffer and for trace data
> + * retention (after crash) only when ETR_MODE_RESRV buffer
> + * mode is enabled. Used by ETF for trace data retention
> + * (after crash) by default.
> */
> struct tmc_drvdata {
> void __iomem *base;
> @@ -211,6 +227,7 @@ struct tmc_drvdata {
> struct mutex idr_mutex;
> struct etr_buf *sysfs_buf;
> struct etr_buf *perf_buf;
> + struct tmc_resrv_buf crash_tbuf;
> };
>
> struct etr_buf_operations {
> @@ -328,6 +345,16 @@ tmc_sg_table_buf_size(struct tmc_sg_table *sg_table)
> return (unsigned long)sg_table->data_pages.nr_pages << PAGE_SHIFT;
> }
>
> +static inline bool is_tmc_reserved_region_valid(struct device *dev)
> +{
> + struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
> +
> + if (drvdata->crash_tbuf.paddr &&
> + drvdata->crash_tbuf.size)
> + return true;
> + return false;
> +}
> +
> struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
>
> void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 3/7] coresight: core: Add provision for panic callbacks
2024-05-31 4:27 ` [PATCH v8 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
@ 2024-05-31 10:07 ` James Clark
0 siblings, 0 replies; 16+ messages in thread
From: James Clark @ 2024-05-31 10:07 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> Panic callback handlers allows coresight device drivers to sync
> relevant trace data and trace metadata to reserved memory
> regions so that they can be retrieved later in the subsequent
> boot or in the crashdump kernel.
>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
Reviewed-by: James Clark <james.clark@arm.com>
> drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++++++++
> include/linux/coresight.h | 12 +++++++
> 2 files changed, 49 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index b83613e34289..61d75aad476b 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -19,6 +19,7 @@
> #include <linux/property.h>
> #include <linux/delay.h>
> #include <linux/pm_runtime.h>
> +#include <linux/panic_notifier.h>
>
> #include "coresight-etm-perf.h"
> #include "coresight-priv.h"
> @@ -1365,6 +1366,36 @@ const struct bus_type coresight_bustype = {
> .name = "coresight",
> };
>
> +static int coresight_panic_sync(struct device *dev, void *data)
> +{
> + int mode;
> + struct coresight_device *csdev;
> +
> + /* Run through panic sync handlers for all enabled devices */
> + csdev = container_of(dev, struct coresight_device, dev);
> + mode = coresight_get_mode(csdev);
> +
> + if ((mode == CS_MODE_SYSFS) || (mode == CS_MODE_PERF)) {
> + if (panic_ops(csdev))
> + panic_ops(csdev)->sync(csdev);
> + }
> +
> + return 0;
> +}
> +
> +static int coresight_panic_cb(struct notifier_block *self,
> + unsigned long v, void *p)
> +{
> + bus_for_each_dev(&coresight_bustype, NULL, NULL,
> + coresight_panic_sync);
> +
> + return 0;
> +}
> +
> +static struct notifier_block coresight_notifier = {
> + .notifier_call = coresight_panic_cb,
> +};
> +
> static int __init coresight_init(void)
> {
> int ret;
> @@ -1377,6 +1408,10 @@ static int __init coresight_init(void)
> if (ret)
> goto exit_bus_unregister;
>
> + /* Register function to be called for panic */
> + ret = atomic_notifier_chain_register(&panic_notifier_list,
> + &coresight_notifier);
> +
> /* initialise the coresight syscfg API */
> ret = cscfg_init();
> if (!ret)
> @@ -1391,6 +1426,8 @@ static int __init coresight_init(void)
> static void __exit coresight_exit(void)
> {
> cscfg_exit();
> + atomic_notifier_chain_unregister(&panic_notifier_list,
> + &coresight_notifier);
> etm_perf_exit();
> bus_unregister(&coresight_bustype);
> }
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 5f288d475490..b156467c9baa 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -315,6 +315,7 @@ enum cs_mode {
> #define link_ops(csdev) csdev->ops->link_ops
> #define helper_ops(csdev) csdev->ops->helper_ops
> #define ect_ops(csdev) csdev->ops->ect_ops
> +#define panic_ops(csdev) csdev->ops->panic_ops
>
> /**
> * struct coresight_ops_sink - basic operations for a sink
> @@ -384,11 +385,22 @@ struct coresight_ops_helper {
> int (*disable)(struct coresight_device *csdev, void *data);
> };
>
> +
> +/**
> + * struct coresight_ops_panic - Generic device ops for panic handing
> + *
> + * @sync : Sync the device register state/trace data
> + */
> +struct coresight_ops_panic {
> + int (*sync)(struct coresight_device *csdev);
> +};
> +
> struct coresight_ops {
> const struct coresight_ops_sink *sink_ops;
> const struct coresight_ops_link *link_ops;
> const struct coresight_ops_source *source_ops;
> const struct coresight_ops_helper *helper_ops;
> + const struct coresight_ops_panic *panic_ops;
> };
>
> static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 4/7] coresight: tmc: Enable panic sync handling
2024-05-31 4:27 ` [PATCH v8 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
@ 2024-05-31 10:10 ` James Clark
0 siblings, 0 replies; 16+ messages in thread
From: James Clark @ 2024-05-31 10:10 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> - Get reserved region from device tree node for metadata
> - Define metadata format for TMC
> - Add TMC ETR panic sync handler that syncs register snapshot
> to metadata region
> - Add TMC ETF panic sync handler that syncs register snapshot
> to metadata region and internal SRAM to reserved trace buffer
> region.
>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: James Clark <james.clark@arm.com>
> ---
> Changelog from v7:
> Avoided a redundant memcpy in tmc_panic_sync_etf.
>
> .../hwtracing/coresight/coresight-tmc-core.c | 25 +++++++
> .../hwtracing/coresight/coresight-tmc-etf.c | 72 +++++++++++++++++++
> .../hwtracing/coresight/coresight-tmc-etr.c | 70 ++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tmc.h | 45 +++++++++++-
> 4 files changed, 211 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index 1325387d6257..7170416c3e1a 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -413,6 +413,31 @@ static void tmc_get_reserved_region(struct device *parent)
>
> drvdata->crash_tbuf.paddr = res.start;
> drvdata->crash_tbuf.size = resource_size(&res);
> +
> + /* Metadata region */
> + node = tmc_get_region_byname(parent->of_node, "metadata");
> + if (IS_ERR_OR_NULL(node)) {
> + dev_dbg(parent, "No metadata memory-region specified\n");
> + return;
> + }
> +
> + rc = of_address_to_resource(node, 0, &res);
> + of_node_put(node);
> + if (rc || res.start == 0 || resource_size(&res) == 0) {
> + dev_err(parent, "Metadata memory is invalid\n");
> + return;
> + }
> +
> + drvdata->crash_mdata.vaddr = memremap(res.start,
> + resource_size(&res),
> + MEMREMAP_WC);
> + if (IS_ERR_OR_NULL(drvdata->crash_mdata.vaddr)) {
> + dev_err(parent, "Metadata memory mapping failed\n");
> + return;
> + }
> +
> + drvdata->crash_mdata.paddr = res.start;
> + drvdata->crash_mdata.size = resource_size(&res);
> }
>
> /* Detect and initialise the capabilities of a TMC ETR */
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index d4f641cd9de6..f9569585e9f8 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -590,6 +590,73 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
> return to_read;
> }
>
> +static int tmc_panic_sync_etf(struct coresight_device *csdev)
> +{
> + u32 val;
> + struct csdev_access *csa;
> + struct tmc_crash_metadata *mdata;
> + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + csa = &drvdata->csdev->access;
> +
> + /* Make sure we have valid reserved memory */
> + if (!is_tmc_reserved_region_valid(csdev->dev.parent))
> + return 0;
> +
> + mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
> + mdata->valid = false;
> +
> + CS_UNLOCK(drvdata->base);
> +
> + /* Proceed only if ETF is enabled or configured as sink */
> + val = readl(drvdata->base + TMC_CTL);
> + if (!(val & TMC_CTL_CAPT_EN))
> + goto out;
> +
> + val = readl(drvdata->base + TMC_MODE);
> + if (val != TMC_MODE_CIRCULAR_BUFFER)
> + goto out;
> +
> + val = readl(drvdata->base + TMC_FFSR);
> + /* Do manual flush and stop only if its not auto-stopped */
> + if (!(val & TMC_FFSR_FT_STOPPED)) {
> + dev_info(&csdev->dev,
> + "%s: Triggering manual flush\n", __func__);
> + tmc_flush_and_stop(drvdata);
> + } else
> + tmc_wait_for_tmcready(drvdata);
> +
> + /* Sync registers from hardware to metadata region */
> + mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS);
> + mdata->trc_paddr = drvdata->crash_tbuf.paddr;
> +
> + /* Sync Internal SRAM to reserved trace buffer region */
> + drvdata->buf = drvdata->crash_tbuf.vaddr;
> + tmc_etb_dump_hw(drvdata);
> + /* Store as per RSZ register convention */
> + mdata->size = drvdata->len >> 2;
> +
> + /*
> + * Make sure all previous writes are completed,
> + * before we mark valid
> + */
> + dsb(sy);
> + mdata->valid = true;
> + /*
> + * Below order need to maintained, since crc of metadata
> + * is dependent on first
> + */
> + mdata->crc32_tdata = find_crash_tracedata_crc(drvdata, mdata);
> + mdata->crc32_mdata = find_crash_metadata_crc(mdata);
> +
> + tmc_disable_hw(drvdata);
> +
> + dev_info(&csdev->dev, "%s: success\n", __func__);
> +out:
> + CS_UNLOCK(drvdata->base);
> + return 0;
> +}
> +
> static const struct coresight_ops_sink tmc_etf_sink_ops = {
> .enable = tmc_enable_etf_sink,
> .disable = tmc_disable_etf_sink,
> @@ -603,6 +670,10 @@ static const struct coresight_ops_link tmc_etf_link_ops = {
> .disable = tmc_disable_etf_link,
> };
>
> +static const struct coresight_ops_panic tmc_etf_sync_ops = {
> + .sync = tmc_panic_sync_etf,
> +};
> +
> const struct coresight_ops tmc_etb_cs_ops = {
> .sink_ops = &tmc_etf_sink_ops,
> };
> @@ -610,6 +681,7 @@ const struct coresight_ops tmc_etb_cs_ops = {
> const struct coresight_ops tmc_etf_cs_ops = {
> .sink_ops = &tmc_etf_sink_ops,
> .link_ops = &tmc_etf_link_ops,
> + .panic_ops = &tmc_etf_sync_ops,
> };
>
> int tmc_read_prepare_etb(struct tmc_drvdata *drvdata)
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 041c428dd7cd..be1079e8fd64 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1813,6 +1813,71 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
> return 0;
> }
>
> +static int tmc_panic_sync_etr(struct coresight_device *csdev)
> +{
> + u32 val;
> + struct csdev_access *csa;
> + struct tmc_crash_metadata *mdata;
> + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + csa = &drvdata->csdev->access;
> +
> + if (!drvdata->etr_buf)
> + return 0;
> +
> + /* Being in RESRV mode implies valid reserved memory as well */
> + if (drvdata->etr_buf->mode != ETR_MODE_RESRV)
> + return 0;
> +
> + mdata = (struct tmc_crash_metadata *)drvdata->crash_mdata.vaddr;
> + mdata->valid = false;
> +
> + CS_UNLOCK(drvdata->base);
> +
> + /* Proceed only if ETR is enabled */
> + val = readl(drvdata->base + TMC_CTL);
> + if (!(val & TMC_CTL_CAPT_EN))
> + goto out;
> +
> + val = readl(drvdata->base + TMC_FFSR);
> + /* Do manual flush and stop only if its not auto-stopped */
> + if (!(val & TMC_FFSR_FT_STOPPED)) {
> + dev_info(&csdev->dev,
> + "%s: Triggering manual flush\n", __func__);
> + tmc_flush_and_stop(drvdata);
> + } else
> + tmc_wait_for_tmcready(drvdata);
> +
> + /* Sync registers from hardware to metadata region */
> + mdata->size = csdev_access_relaxed_read32(csa, TMC_RSZ);
> + mdata->sts = csdev_access_relaxed_read32(csa, TMC_STS);
> + mdata->rrp = tmc_read_rrp(drvdata);
> + mdata->rwp = tmc_read_rwp(drvdata);
> + mdata->dba = tmc_read_dba(drvdata);
> + mdata->trc_paddr = drvdata->crash_tbuf.paddr;
> +
> + /*
> + * Make sure all previous writes are completed,
> + * before we mark valid
> + */
> + dsb(sy);
> + mdata->valid = true;
> + /*
> + * Below order need to maintained, since crc of metadata
> + * is dependent on first
> + */
> + mdata->crc32_tdata = find_crash_tracedata_crc(drvdata, mdata);
> + mdata->crc32_mdata = find_crash_metadata_crc(mdata);
> +
> + tmc_disable_hw(drvdata);
> +
> + dev_info(&csdev->dev, "%s: success\n", __func__);
> +out:
> + CS_UNLOCK(drvdata->base);
> +
> + return 0;
> +}
> +
> static const struct coresight_ops_sink tmc_etr_sink_ops = {
> .enable = tmc_enable_etr_sink,
> .disable = tmc_disable_etr_sink,
> @@ -1821,8 +1886,13 @@ static const struct coresight_ops_sink tmc_etr_sink_ops = {
> .free_buffer = tmc_free_etr_buffer,
> };
>
> +static const struct coresight_ops_panic tmc_etr_sync_ops = {
> + .sync = tmc_panic_sync_etr,
> +};
> +
> const struct coresight_ops tmc_etr_cs_ops = {
> .sink_ops = &tmc_etr_sink_ops,
> + .panic_ops = &tmc_etr_sync_ops,
> };
>
> int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 2abc5387cdf7..875d4129da7c 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -12,6 +12,7 @@
> #include <linux/miscdevice.h>
> #include <linux/mutex.h>
> #include <linux/refcount.h>
> +#include <linux/crc32.h>
>
> #define TMC_RSZ 0x004
> #define TMC_STS 0x00c
> @@ -76,6 +77,9 @@
> #define TMC_AXICTL_AXCACHE_OS (0xf << 2)
> #define TMC_AXICTL_ARCACHE_OS (0xf << 16)
>
> +/* TMC_FFSR - 0x300 */
> +#define TMC_FFSR_FT_STOPPED BIT(1)
> +
> /* TMC_FFCR - 0x304 */
> #define TMC_FFCR_FLUSHMAN_BIT 6
> #define TMC_FFCR_EN_FMT BIT(0)
> @@ -131,6 +135,21 @@ enum tmc_mem_intf_width {
> #define CORESIGHT_SOC_600_ETR_CAPS \
> (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
>
> +/* TMC metadata region for ETR and ETF configurations */
> +struct tmc_crash_metadata {
> + uint32_t crc32_mdata; /* crc of metadata */
> + uint32_t crc32_tdata; /* crc of tracedata */
> + uint32_t valid; /* Indicate if this ETF/ETR was enabled */
> + uint32_t size; /* Ram Size register */
> + uint32_t sts; /* Status register */
> + uint32_t reserved32[3];
> + uint64_t rrp; /* Ram Read pointer register */
> + uint64_t rwp; /* Ram Write pointer register */
> + uint64_t dba; /* Data buffer address register */
> + uint64_t trc_paddr; /* Phys address of trace buffer */
> + uint64_t reserved64[3];
> +};
> +
> enum etr_mode {
> ETR_MODE_FLAT, /* Uses contiguous flat buffer */
> ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
> @@ -203,6 +222,8 @@ struct tmc_resrv_buf {
> * retention (after crash) only when ETR_MODE_RESRV buffer
> * mode is enabled. Used by ETF for trace data retention
> * (after crash) by default.
> + * @crash_mdata: Reserved memory for storing tmc crash metadata.
> + * Used by ETR/ETF.
> */
> struct tmc_drvdata {
> void __iomem *base;
> @@ -228,6 +249,7 @@ struct tmc_drvdata {
> struct etr_buf *sysfs_buf;
> struct etr_buf *perf_buf;
> struct tmc_resrv_buf crash_tbuf;
> + struct tmc_resrv_buf crash_mdata;
> };
>
> struct etr_buf_operations {
> @@ -350,11 +372,32 @@ static inline bool is_tmc_reserved_region_valid(struct device *dev)
> struct tmc_drvdata *drvdata = dev_get_drvdata(dev);
>
> if (drvdata->crash_tbuf.paddr &&
> - drvdata->crash_tbuf.size)
> + drvdata->crash_tbuf.size &&
> + drvdata->crash_mdata.paddr &&
> + drvdata->crash_mdata.size)
> return true;
> return false;
> }
>
> +static inline uint32_t find_crash_metadata_crc(struct tmc_crash_metadata *md)
> +{
> + unsigned long crc_size;
> +
> + crc_size = sizeof(struct tmc_crash_metadata) -
> + offsetof(struct tmc_crash_metadata, crc32_tdata);
> + return crc32_le(0, (void *)&md->crc32_tdata, crc_size);
> +}
> +
> +static inline uint32_t find_crash_tracedata_crc(struct tmc_drvdata *drvdata,
> + struct tmc_crash_metadata *md)
> +{
> + unsigned long crc_size;
> +
> + /* Take CRC of configured buffer size to keep it simple */
> + crc_size = md->size << 2;
> + return crc32_le(0, (void *)drvdata->crash_tbuf.vaddr, crc_size);
> +}
> +
> struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvdata);
>
> void tmc_etr_set_catu_ops(const struct etr_buf_operations *catu);
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn
2024-05-31 4:27 ` [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
@ 2024-05-31 10:16 ` James Clark
2024-06-05 4:44 ` [EXTERNAL] " Linu Cherian
0 siblings, 1 reply; 16+ messages in thread
From: James Clark @ 2024-05-31 10:16 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> Configure TMC ETR and ETF to flush and stop trace capture
> on FlIn event based on sysfs attribute,
> /sys/bus/coresight/devices/tmc_etXn/stop_on_flush.
>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
> Changelog from v7:
> * Honour stop_on_flush sysfs attribute for perf sessions as well.
> This allows user to start trace sessions using perf method as
> well to use the Coresight kernel panic support.
>
> .../hwtracing/coresight/coresight-tmc-core.c | 31 +++++++++++++++++++
> .../hwtracing/coresight/coresight-tmc-etf.c | 18 ++++++++---
> .../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++---
> drivers/hwtracing/coresight/coresight-tmc.h | 4 +++
> 4 files changed, 61 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index aaa9de9f4cd2..24edd9d750c3 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -452,9 +452,40 @@ static ssize_t buffer_size_store(struct device *dev,
>
> static DEVICE_ATTR_RW(buffer_size);
>
> +static ssize_t stop_on_flush_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + return sprintf(buf, "%#x\n", drvdata->stop_on_flush);
> +}
> +
> +static ssize_t stop_on_flush_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + int ret;
> + u8 val;
> + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + ret = kstrtou8(buf, 0, &val);
> + if (ret)
> + return ret;
> + if (val)
> + drvdata->stop_on_flush = true;
> + else
> + drvdata->stop_on_flush = false;
> +
> + return size;
> +}
> +
> +static DEVICE_ATTR_RW(stop_on_flush);
> +
> +
> static struct attribute *coresight_tmc_attrs[] = {
> &dev_attr_trigger_cntr.attr,
> &dev_attr_buffer_size.attr,
> + &dev_attr_stop_on_flush.attr,
> NULL,
> };
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> index 655c0c0ba54b..1529b9cc210a 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> @@ -19,6 +19,7 @@ static int tmc_set_etf_buffer(struct coresight_device *csdev,
> static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
> {
> int rc = 0;
> + u32 ffcr;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -32,10 +33,12 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
> }
>
> writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
> - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
> - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
> - TMC_FFCR_TRIGON_TRIGIN,
> - drvdata->base + TMC_FFCR);
> +
> + ffcr = TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN |
> + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN;
> + if (drvdata->stop_on_flush_en)
> + ffcr |= TMC_FFCR_STOP_ON_FLUSH;
> + writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
>
> writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
> tmc_enable_hw(drvdata);
> @@ -225,7 +228,8 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_device *csdev)
> used = true;
> drvdata->buf = buf;
> }
> -
> + if (drvdata->stop_on_flush)
> + drvdata->stop_on_flush_en = true;
Does this do anything different than only using stop_on_flush in
__tmc_etr_enable_hw()?
Seems like stop_on_flush_en == stop_on_flush whenever stop_on_flush_en
is read, so you might as well just read stop_on_flush and get rid of the
_en copy?
> ret = tmc_etb_enable_hw(drvdata);
> if (!ret) {
> coresight_set_mode(csdev, CS_MODE_SYSFS);
> @@ -288,6 +292,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data)
> break;
> }
>
> + if (drvdata->stop_on_flush)
> + drvdata->stop_on_flush_en = true;
> ret = tmc_etb_enable_hw(drvdata);
> if (!ret) {
> /* Associate with monitored process. */
> @@ -349,6 +355,8 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev)
> tmc_etb_disable_hw(drvdata);
> /* Dissociate from monitored process. */
> drvdata->pid = -1;
> + /* Reset stop on flush */
> + drvdata->stop_on_flush_en = false;
> coresight_set_mode(csdev, CS_MODE_DISABLED);
>
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index 74f53972ce3c..bf2d0932e205 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1059,7 +1059,7 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
>
> static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> {
> - u32 axictl, sts;
> + u32 axictl, sts, ffcr;
> struct etr_buf *etr_buf = drvdata->etr_buf;
> int rc = 0;
>
> @@ -1105,10 +1105,12 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> writel_relaxed(sts, drvdata->base + TMC_STS);
> }
>
> - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
> - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
> - TMC_FFCR_TRIGON_TRIGIN,
> - drvdata->base + TMC_FFCR);
> + ffcr = TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN |
> + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN;
> + if (drvdata->stop_on_flush_en)
> + ffcr |= TMC_FFCR_STOP_ON_FLUSH;
> + writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
> +
> writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
> tmc_enable_hw(drvdata);
>
> @@ -1313,6 +1315,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
> goto out;
> }
>
> + if (drvdata->stop_on_flush)
> + drvdata->stop_on_flush_en = true;
> ret = tmc_etr_enable_hw(drvdata, sysfs_buf);
> if (!ret) {
> coresight_set_mode(csdev, CS_MODE_SYSFS);
> @@ -1758,6 +1762,8 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data)
> goto unlock_out;
> }
>
> + if (drvdata->stop_on_flush)
> + drvdata->stop_on_flush_en = true;
> rc = tmc_etr_enable_hw(drvdata, etr_perf->etr_buf);
> if (!rc) {
> /* Associate with monitored process. */
> @@ -1808,6 +1814,8 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
> tmc_etr_disable_hw(drvdata);
> /* Dissociate from monitored process. */
> drvdata->pid = -1;
> + /* Reset stop on flush */
> + drvdata->stop_on_flush_en = false;
> coresight_set_mode(csdev, CS_MODE_DISABLED);
> /* Reset perf specific data */
> drvdata->perf_buf = NULL;
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 528174283ecc..81eadb384b83 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -205,6 +205,8 @@ struct tmc_resrv_buf {
> * @spinlock: only one at a time pls.
> * @pid: Process ID of the process being monitored by the session
> * that is using this component.
> + * @stop_on_flush: Stop on flush trigger user configuration.
> + * @stop_on_flush_en: Stop on flush enable flag
> * @buf: Snapshot of the trace data for ETF/ETB.
> * @etr_buf: details of buffer used in TMC-ETR
> * @len: size of the available trace for ETF/ETB.
> @@ -238,6 +240,8 @@ struct tmc_drvdata {
> spinlock_t spinlock;
> pid_t pid;
> bool reading;
> + bool stop_on_flush;
> + bool stop_on_flush_en;
> union {
> char *buf; /* TMC ETB */
> struct etr_buf *etr_buf; /* TMC ETR */
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v8 7/7] coresight: config: Add preloaded configuration
2024-05-31 4:27 ` [PATCH v8 7/7] coresight: config: Add preloaded configuration Linu Cherian
@ 2024-05-31 10:19 ` James Clark
0 siblings, 0 replies; 16+ messages in thread
From: James Clark @ 2024-05-31 10:19 UTC (permalink / raw)
To: Linu Cherian
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree, sgoutham, gcherian,
suzuki.poulose, mike.leach
On 31/05/2024 05:27, Linu Cherian wrote:
> Add a preloaded configuration for generating
> external trigger on address match. This can be
> used by CTI and ETR blocks to stop trace capture
> on kernel panic.
>
> Kernel address for "panic" function is used as the
> default trigger address.
>
> This new configuration is available as,
> /sys/kernel/config/cs-syscfg/configurations/panicstop
>
Reviewed-by: James Clark <james.clark@arm.com>
> Signed-off-by: Linu Cherian <lcherian@marvell.com>
> ---
> drivers/hwtracing/coresight/Makefile | 2 +-
> .../coresight/coresight-cfg-preload.c | 2 +
> .../coresight/coresight-cfg-preload.h | 2 +
> .../hwtracing/coresight/coresight-cfg-pstop.c | 83 +++++++++++++++++++
> 4 files changed, 88 insertions(+), 1 deletion(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-cfg-pstop.c
>
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 4ba478211b31..46ce7f39d05f 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -25,7 +25,7 @@ subdir-ccflags-y += $(condflags)
> obj-$(CONFIG_CORESIGHT) += coresight.o
> coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
> coresight-sysfs.o coresight-syscfg.o coresight-config.o \
> - coresight-cfg-preload.o coresight-cfg-afdo.o \
> + coresight-cfg-preload.o coresight-cfg-afdo.o coresight-cfg-pstop.o \
> coresight-syscfg-configfs.o coresight-trace-id.o
> obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
> coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
> diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.c b/drivers/hwtracing/coresight/coresight-cfg-preload.c
> index e237a4edfa09..4980e68483c5 100644
> --- a/drivers/hwtracing/coresight/coresight-cfg-preload.c
> +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.c
> @@ -13,6 +13,7 @@
> static struct cscfg_feature_desc *preload_feats[] = {
> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
> &strobe_etm4x,
> + &gen_etrig_etm4x,
> #endif
> NULL
> };
> @@ -20,6 +21,7 @@ static struct cscfg_feature_desc *preload_feats[] = {
> static struct cscfg_config_desc *preload_cfgs[] = {
> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
> &afdo_etm4x,
> + &pstop_etm4x,
> #endif
> NULL
> };
> diff --git a/drivers/hwtracing/coresight/coresight-cfg-preload.h b/drivers/hwtracing/coresight/coresight-cfg-preload.h
> index 21299e175477..291ba530a6a5 100644
> --- a/drivers/hwtracing/coresight/coresight-cfg-preload.h
> +++ b/drivers/hwtracing/coresight/coresight-cfg-preload.h
> @@ -10,4 +10,6 @@
> #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
> extern struct cscfg_feature_desc strobe_etm4x;
> extern struct cscfg_config_desc afdo_etm4x;
> +extern struct cscfg_feature_desc gen_etrig_etm4x;
> +extern struct cscfg_config_desc pstop_etm4x;
> #endif
> diff --git a/drivers/hwtracing/coresight/coresight-cfg-pstop.c b/drivers/hwtracing/coresight/coresight-cfg-pstop.c
> new file mode 100644
> index 000000000000..c2bfbd07bfaf
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-cfg-pstop.c
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright(C) 2023 Marvell.
> + * Based on coresight-cfg-afdo.c
> + */
> +
> +#include "coresight-config.h"
> +
> +/* ETMv4 includes and features */
> +#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
> +#include "coresight-etm4x-cfg.h"
> +
> +/* preload configurations and features */
> +
> +/* preload in features for ETMv4 */
> +
> +/* panic_stop feature */
> +static struct cscfg_parameter_desc gen_etrig_params[] = {
> + {
> + .name = "address",
> + .value = (u64)panic,
> + },
> +};
> +
> +static struct cscfg_regval_desc gen_etrig_regs[] = {
> + /* resource selector */
> + {
> + .type = CS_CFG_REG_TYPE_RESOURCE,
> + .offset = TRCRSCTLRn(2),
> + .hw_info = ETM4_CFG_RES_SEL,
> + .val32 = 0x40001,
> + },
> + /* single address comparator */
> + {
> + .type = CS_CFG_REG_TYPE_RESOURCE | CS_CFG_REG_TYPE_VAL_64BIT |
> + CS_CFG_REG_TYPE_VAL_PARAM,
> + .offset = TRCACVRn(0),
> + .val32 = 0x0,
> + },
> + {
> + .type = CS_CFG_REG_TYPE_RESOURCE,
> + .offset = TRCACATRn(0),
> + .val64 = 0xf00,
> + },
> + /* Driver external output[0] with comparator out */
> + {
> + .type = CS_CFG_REG_TYPE_RESOURCE,
> + .offset = TRCEVENTCTL0R,
> + .val32 = 0x2,
> + },
> + /* end of regs */
> +};
> +
> +struct cscfg_feature_desc gen_etrig_etm4x = {
> + .name = "gen_etrig",
> + .description = "Generate external trigger on address match\n"
> + "parameter \'address\': address of kernel address\n",
> + .match_flags = CS_CFG_MATCH_CLASS_SRC_ETM4,
> + .nr_params = ARRAY_SIZE(gen_etrig_params),
> + .params_desc = gen_etrig_params,
> + .nr_regs = ARRAY_SIZE(gen_etrig_regs),
> + .regs_desc = gen_etrig_regs,
> +};
> +
> +/* create a panic stop configuration */
> +
> +/* the total number of parameters in used features */
> +#define PSTOP_NR_PARAMS ARRAY_SIZE(gen_etrig_params)
> +
> +static const char *pstop_ref_names[] = {
> + "gen_etrig",
> +};
> +
> +struct cscfg_config_desc pstop_etm4x = {
> + .name = "panicstop",
> + .description = "Stop ETM on kernel panic\n",
> + .nr_feat_refs = ARRAY_SIZE(pstop_ref_names),
> + .feat_ref_names = pstop_ref_names,
> + .nr_total_params = PSTOP_NR_PARAMS,
> +};
> +
> +/* end of ETM4x configurations */
> +#endif /* IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X) */
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [EXTERNAL] Re: [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn
2024-05-31 10:16 ` James Clark
@ 2024-06-05 4:44 ` Linu Cherian
0 siblings, 0 replies; 16+ messages in thread
From: Linu Cherian @ 2024-06-05 4:44 UTC (permalink / raw)
To: James Clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree,
Sunil Kovvuri Goutham, George Cherian, suzuki.poulose,
mike.leach
Hi James,
> -----Original Message-----
> From: James Clark <james.clark@arm.com>
> Sent: Friday, May 31, 2024 3:47 PM
> To: Linu Cherian <lcherian@marvell.com>
> Cc: linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux-
> kernel@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> devicetree@vger.kernel.org; Sunil Kovvuri Goutham
> <sgoutham@marvell.com>; George Cherian <gcherian@marvell.com>;
> suzuki.poulose@arm.com; mike.leach@linaro.org
> Subject: [EXTERNAL] Re: [PATCH v8 6/7] coresight: tmc: Stop trace capture on
> FlIn
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
>
>
> On 31/05/2024 05:27, Linu Cherian wrote:
> > Configure TMC ETR and ETF to flush and stop trace capture on FlIn
> > event based on sysfs attribute,
> > /sys/bus/coresight/devices/tmc_etXn/stop_on_flush.
> >
> > Signed-off-by: Linu Cherian <lcherian@marvell.com>
> > ---
> > Changelog from v7:
> > * Honour stop_on_flush sysfs attribute for perf sessions as well.
> > This allows user to start trace sessions using perf method as
> > well to use the Coresight kernel panic support.
> >
> > .../hwtracing/coresight/coresight-tmc-core.c | 31
> +++++++++++++++++++
> > .../hwtracing/coresight/coresight-tmc-etf.c | 18 ++++++++---
> > .../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++---
> > drivers/hwtracing/coresight/coresight-tmc.h | 4 +++
> > 4 files changed, 61 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c
> > b/drivers/hwtracing/coresight/coresight-tmc-core.c
> > index aaa9de9f4cd2..24edd9d750c3 100644
> > --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> > +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> > @@ -452,9 +452,40 @@ static ssize_t buffer_size_store(struct device
> > *dev,
> >
> > static DEVICE_ATTR_RW(buffer_size);
> >
> > +static ssize_t stop_on_flush_show(struct device *dev,
> > + struct device_attribute *attr, char *buf) {
> > + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +
> > + return sprintf(buf, "%#x\n", drvdata->stop_on_flush); }
> > +
> > +static ssize_t stop_on_flush_store(struct device *dev,
> > + struct device_attribute *attr,
> > + const char *buf, size_t size)
> > +{
> > + int ret;
> > + u8 val;
> > + struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > +
> > + ret = kstrtou8(buf, 0, &val);
> > + if (ret)
> > + return ret;
> > + if (val)
> > + drvdata->stop_on_flush = true;
> > + else
> > + drvdata->stop_on_flush = false;
> > +
> > + return size;
> > +}
> > +
> > +static DEVICE_ATTR_RW(stop_on_flush);
> > +
> > +
> > static struct attribute *coresight_tmc_attrs[] = {
> > &dev_attr_trigger_cntr.attr,
> > &dev_attr_buffer_size.attr,
> > + &dev_attr_stop_on_flush.attr,
> > NULL,
> > };
> >
> > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > index 655c0c0ba54b..1529b9cc210a 100644
> > --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > @@ -19,6 +19,7 @@ static int tmc_set_etf_buffer(struct
> > coresight_device *csdev, static int __tmc_etb_enable_hw(struct
> > tmc_drvdata *drvdata) {
> > int rc = 0;
> > + u32 ffcr;
> >
> > CS_UNLOCK(drvdata->base);
> >
> > @@ -32,10 +33,12 @@ static int __tmc_etb_enable_hw(struct
> tmc_drvdata *drvdata)
> > }
> >
> > writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base +
> TMC_MODE);
> > - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
> > - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
> > - TMC_FFCR_TRIGON_TRIGIN,
> > - drvdata->base + TMC_FFCR);
> > +
> > + ffcr = TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
> TMC_FFCR_FON_FLIN |
> > + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN;
> > + if (drvdata->stop_on_flush_en)
> > + ffcr |= TMC_FFCR_STOP_ON_FLUSH;
> > + writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
> >
> > writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
> > tmc_enable_hw(drvdata);
> > @@ -225,7 +228,8 @@ static int tmc_enable_etf_sink_sysfs(struct
> coresight_device *csdev)
> > used = true;
> > drvdata->buf = buf;
> > }
> > -
> > + if (drvdata->stop_on_flush)
> > + drvdata->stop_on_flush_en = true;
>
> Does this do anything different than only using stop_on_flush in
> __tmc_etr_enable_hw()?
>
> Seems like stop_on_flush_en == stop_on_flush whenever
> stop_on_flush_en is read, so you might as well just read stop_on_flush and
> get rid of the _en copy?
>
Ack.
^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [EXTERNAL] Re: [PATCH v8 5/7] coresight: tmc: Add support for reading crash data
2024-05-31 10:03 ` James Clark
@ 2024-06-05 4:46 ` Linu Cherian
0 siblings, 0 replies; 16+ messages in thread
From: Linu Cherian @ 2024-06-05 4:46 UTC (permalink / raw)
To: James Clark
Cc: linux-arm-kernel, coresight, linux-kernel, robh+dt,
krzysztof.kozlowski+dt, conor+dt, devicetree,
Sunil Kovvuri Goutham, George Cherian, Anil Kumar Reddy H,
Tanmay Jagdale, suzuki.poulose, mike.leach
Hi James,
> -----Original Message-----
> From: James Clark <james.clark@arm.com>
> Sent: Friday, May 31, 2024 3:33 PM
> To: Linu Cherian <lcherian@marvell.com>
> Cc: linux-arm-kernel@lists.infradead.org; coresight@lists.linaro.org; linux-
> kernel@vger.kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org; conor+dt@kernel.org;
> devicetree@vger.kernel.org; Sunil Kovvuri Goutham
> <sgoutham@marvell.com>; George Cherian <gcherian@marvell.com>; Anil
> Kumar Reddy H <areddy3@marvell.com>; Tanmay Jagdale
> <tanmay@marvell.com>; suzuki.poulose@arm.com; mike.leach@linaro.org
> Subject: [EXTERNAL] Re: [PATCH v8 5/7] coresight: tmc: Add support for
> reading crash data
>
> Prioritize security for external emails: Confirm sender and content safety
> before clicking links or opening attachments
>
> ----------------------------------------------------------------------
>
>
> On 31/05/2024 05:27, Linu Cherian wrote:
> > * Introduce a new mode CS_MODE_READ_CRASHDATA for reading trace
> > captured in previous crash/watchdog reset.
> >
> > * Add special device files for reading ETR/ETF crash data.
> >
> > * User can read the crash data as below
> >
> > For example, for reading crash data from tmc_etf sink
> >
> > #dd if=/dev/crash_tmc_etfXX of=~/cstrace.bin
> >
> > Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
> > Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> > Signed-off-by: Linu Cherian <lcherian@marvell.com>
> > ---
> > Changelog from v7:
> > * Moved crash dev registration into new function,
> > register_crash_dev_interface
> > * Removed redundant variable trace_addr in
> > tmc_etr_setup_crashdata_buf
> >
> > .../coresight/coresight-etm4x-core.c | 1 +
> > .../hwtracing/coresight/coresight-tmc-core.c | 148 ++++++++++++++++-
> > .../hwtracing/coresight/coresight-tmc-etf.c | 73 +++++++++
> > .../hwtracing/coresight/coresight-tmc-etr.c | 152 +++++++++++++++++-
> > drivers/hwtracing/coresight/coresight-tmc.h | 11 +-
> > include/linux/coresight.h | 13 ++
> > 6 files changed, 391 insertions(+), 7 deletions(-)
> >
>
> [...]
>
> > +static void register_crash_dev_interface(struct tmc_drvdata * drvdata,
> > + const char *name)
> > +{
> > + drvdata->crashdev.name =
> > + devm_kasprintf(&drvdata->csdev->dev, GFP_KERNEL,
> "%s_%s", "crash", name);
> > + drvdata->crashdev.minor = MISC_DYNAMIC_MINOR;
> > + drvdata->crashdev.fops = &tmc_crashdata_fops;
> > + if (misc_register(&drvdata->crashdev))
> > + dev_dbg(&drvdata->csdev->dev,
> > + "Failed to setup user interface for crashdata\n"); }
> > +
> > static int tmc_probe(struct amba_device *adev, const struct amba_id
> > *id) {
> > int ret = 0;
> > @@ -619,6 +752,10 @@ static int tmc_probe(struct amba_device *adev,
> const struct amba_id *id)
> > coresight_unregister(drvdata->csdev);
> > else
> > pm_runtime_put(&adev->dev);
> > +
> > + if (is_tmc_reserved_region_valid(dev))
> > + register_crash_dev_interface(drvdata, desc.name);
> > +
>
> Now that you've added an extra step to the probe you need to add a "goto
> out" when the previous step fails:
>
> if (ret) {
> coresight_unregister(drvdata->csdev);
> + goto out;
> }
>
> That seems to be the pattern in the rest of the function. Otherwise you
> might register the interface on no device.
>
> There's also a conflict here and in some other places. Since this has to go
> through the coresight branch you should base it off of coresight-next.
>
Ack.
> > out:
> > return ret;
> > }
> > @@ -630,7 +767,8 @@ static void tmc_shutdown(struct amba_device
> *adev)
> >
> > spin_lock_irqsave(&drvdata->spinlock, flags);
> >
> > - if (coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED)
> > + if ((coresight_get_mode(drvdata->csdev) == CS_MODE_DISABLED)
> ||
> > + (coresight_get_mode(drvdata->csdev) ==
> CS_MODE_READ_CRASHDATA))
> > goto out;
> >
> > if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) diff --git
> > a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > index f9569585e9f8..655c0c0ba54b 100644
> > --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
> > @@ -657,6 +657,56 @@ static int tmc_panic_sync_etf(struct
> coresight_device *csdev)
> > return 0;
> > }
> >
>
> [...]
>
> > @@ -725,6 +789,7 @@ int tmc_read_prepare_etb(struct tmc_drvdata
> *drvdata)
> > __tmc_etb_disable_hw(drvdata);
> > }
> >
> > +mode_valid:
> > drvdata->reading = true;
> > out:
> > spin_unlock_irqrestore(&drvdata->spinlock, flags); @@ -744,8
> +809,16
> > @@ int tmc_read_unprepare_etb(struct tmc_drvdata *drvdata)
> > drvdata->config_type != TMC_CONFIG_TYPE_ETF))
> > return -EINVAL;
> >
> > +
>
> Whitespace change. There are a couple of other minor checkpatch style
> warnings.
Ack.
>
> The rest looks good to me. All the tests are passing. I still think we should all
> the kself test for this mode, but that can be done later.
Sure. Will add kself tests for sysfs mode and send it as separate patches.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-06-05 4:46 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-31 4:27 [PATCH v8 0/7] Coresight for Kernel panic and watchdog reset Linu Cherian
2024-05-31 4:27 ` [PATCH v8 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property Linu Cherian
2024-05-31 4:27 ` [PATCH v8 2/7] coresight: tmc-etr: Add support to use reserved trace memory Linu Cherian
2024-05-31 10:05 ` James Clark
2024-05-31 4:27 ` [PATCH v8 3/7] coresight: core: Add provision for panic callbacks Linu Cherian
2024-05-31 10:07 ` James Clark
2024-05-31 4:27 ` [PATCH v8 4/7] coresight: tmc: Enable panic sync handling Linu Cherian
2024-05-31 10:10 ` James Clark
2024-05-31 4:27 ` [PATCH v8 5/7] coresight: tmc: Add support for reading crash data Linu Cherian
2024-05-31 10:03 ` James Clark
2024-06-05 4:46 ` [EXTERNAL] " Linu Cherian
2024-05-31 4:27 ` [PATCH v8 6/7] coresight: tmc: Stop trace capture on FlIn Linu Cherian
2024-05-31 10:16 ` James Clark
2024-06-05 4:44 ` [EXTERNAL] " Linu Cherian
2024-05-31 4:27 ` [PATCH v8 7/7] coresight: config: Add preloaded configuration Linu Cherian
2024-05-31 10:19 ` James Clark
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