Re: [PATCH v7 1/2] dt-bindings: phy: Add CIX Sky1 USB3 PHY

[Krzysztof Kozlowski <krzk@kernel.org>]

On 11/11/2026 04:09, Hongliang Yang wrote:
> Add device tree binding for the CIX Sky1 USB3 PHY, the SuperSpeedPlus
> PHY of the two USB3 Type-A ports of the SoC.
> 
> The two lanes are not separate devices: they live in one register
> block, share the same clocks and resets, and are brought up by the
> same initialization sequence. The node is therefore a single PHY
> provider with #phy-cells = <0>, referenced by both controllers, and the
> driver reference counts phy_init() and phy_exit() so that the block is
> set up once for all of them.
> 
> Signed-off-by: Hongliang Yang <hongliang.yang@cixtech.com>
> ---
> Changes in v7:
> - Describe the PHY as one provider of both lanes and say why. v5 had
>   one child node per lane, v6 dropped them, and nothing in the binding
>   or the changelog said where the second lane went.
> - Reword the description so that it describes the provider instead of
>   the register programming of the block.
> 

You gave me exactly 0 minutes to reply to your answer on v6. Nice
process - bury existing comments it with new version, hoping people will
move on. Dropping from DT patchwork as previous issues are not answered.

Best regards,
Krzysztof