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From: Philipp Zabel <p.zabel@pengutronix.de>
To: "Cristian Ciocaltea" <cristian.ciocaltea@collabora.com>,
	"Sandy Huang" <hjc@rock-chips.com>,
	"Heiko Stübner" <heiko@sntech.de>,
	"Andy Yan" <andy.yan@rock-chips.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Andrzej Hajda" <andrzej.hajda@intel.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Robert Foss" <rfoss@kernel.org>,
	"Laurent Pinchart" <Laurent.pinchart@ideasonboard.com>,
	"Jonas Karlman" <jonas@kwiboo.se>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	"Luca Ceresoli" <luca.ceresoli@bootlin.com>
Cc: kernel@collabora.com, Andy Yan <andyshrk@163.com>,
	 dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-rockchip@lists.infradead.org,
	 linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness
Date: Thu, 18 Jun 2026 13:52:05 +0200	[thread overview]
Message-ID: <604a73b122bd5fb7b35fe5bfeb0352bd9fd99046.camel@pengutronix.de> (raw)
In-Reply-To: <302d42b0-108e-4936-bc34-49b9194985f1@collabora.com>

On Do, 2026-06-18 at 14:46 +0300, Cristian Ciocaltea wrote:
> On 6/18/26 12:39 PM, Philipp Zabel wrote:
> > On Mi, 2026-06-17 at 21:51 +0300, Cristian Ciocaltea wrote:
> > > Assert the AXI reset in the CRTC disable path, and the VP DCLK reset in
> > > the enable path.
> > > 
> > > These resets are intended to leave the hardware in a clean state for the
> > > next use, helping recover from exceptions such as IOMMU page faults, as
> > > well as to prevent random display output glitches, such as a blank
> > > image, observed when switching modes that also change the color format,
> > > e.g. from RGB to YUV420 and vice versa.
> > > 
> > > For now this seems to affect only the RK3588, hence the resets are
> > > optional and will be provided in the device tree for this SoC only.
> > > 
> > > Co-developed-by: Andy Yan <andy.yan@rock-chips.com>
> > > Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
> > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> > > ---
> > >  drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 35 ++++++++++++++++++++++++++++
> > >  drivers/gpu/drm/rockchip/rockchip_drm_vop2.h |  4 ++++
> > >  2 files changed, 39 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> > > index 4cce3e336f5b..2833fb49ad81 100644
> > > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> > > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> > > @@ -17,6 +17,7 @@
> > >  #include <linux/platform_device.h>
> > >  #include <linux/pm_runtime.h>
> > >  #include <linux/regmap.h>
> > > +#include <linux/reset.h>
> > >  #include <linux/swab.h>
> > >  
> > >  #include <drm/drm.h>
> > > @@ -860,6 +861,26 @@ static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
> > >  	return ret;
> > >  }
> > >  
> > > +static void vop2_clk_reset(struct vop2 *vop2, struct reset_control *rstc)
> > 
> > The _clk part of the function name is misleading ...
> 
> Ack.  
> 
> We need to make this clearly distinct from another similarly named function,
> vop2_crtc_reset(), hence I'd propose:
> 
> - vop2_reset_assert_deassert()
> - vop2_reset_cycle()
> - vop2_do_reset()
> 
> Any preference / alternative suggestions?

Or vop2_reset_control_reset(). The three above are equally fine.

regards
Philipp

  reply	other threads:[~2026-06-18 11:52 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-17 18:51 [PATCH 0/9] Support 10-bit YUV422 and 8/10-bit YUV420 color format on DW HDMI QP Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 1/9] dt-bindings: display: vop2: Add missing reset properties Cristian Ciocaltea
2026-06-18  7:58   ` Diederik de Haas
2026-06-18  8:39     ` Cristian Ciocaltea
2026-07-03 16:37       ` Heiko Stübner
2026-07-03 16:59         ` Cristian Ciocaltea
2026-06-22 13:25   ` Krzysztof Kozlowski
2026-06-17 18:51 ` [PATCH 2/9] drm/rockchip: vop2: Reset AXI and DCLK to improve robustness Cristian Ciocaltea
2026-06-18  9:39   ` Philipp Zabel
2026-06-18 11:46     ` Cristian Ciocaltea
2026-06-18 11:52       ` Philipp Zabel [this message]
2026-07-05 13:28   ` Diederik de Haas
2026-07-05 20:46     ` Cristian Ciocaltea
2026-07-05 22:20       ` Diederik de Haas
2026-06-17 18:51 ` [PATCH 3/9] drm/rockchip: vop2: Avoid DCLK source switch for 10-bit YUV422 output Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 4/9] drm/rockchip: vop2: Consolidate HDMI PHY PLL clock parent switch Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 5/9] drm/rockchip: vop2: Switch to enum vop_csc_format Cristian Ciocaltea
2026-06-17 18:51 ` [PATCH 6/9] drm/bridge: dw-hdmi-qp: Log resolution and refresh rate in atomic_enable() Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 7/9] drm/rockchip: dw_hdmi_qp: Support 10-bit YUV422 output format Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 8/9] drm/rockchip: dw_hdmi_qp: Enable YUV420 " Cristian Ciocaltea
2026-06-17 18:52 ` [PATCH 9/9] arm64: dts: rockchip: Add RK3588 VOP2 resets Cristian Ciocaltea

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