From: Robert Beckett <bob.beckett@collabora.com>
To: "Thomas Hellström (Intel)" <thomas_os@shipmail.org>,
"Jani Nikula" <jani.nikula@linux.intel.com>,
"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
"David Airlie" <airlied@linux.ie>,
"Daniel Vetter" <daniel@ffwll.ch>
Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH v5 4/5] drm/i915: add gtt misalignment test
Date: Wed, 26 Jan 2022 17:22:51 +0000 [thread overview]
Message-ID: <60c29fb8-06a8-8daa-3cef-092d6b8d0323@collabora.com> (raw)
In-Reply-To: <b6e9a900-435f-148c-826f-a8f6c188df94@shipmail.org>
On 26/01/2022 14:05, Thomas Hellström (Intel) wrote:
>
> On 1/25/22 20:35, Robert Beckett wrote:
>> add test to check handling of misaligned offsets and sizes
>>
>> v4:
>> * remove spurious blank lines
>> * explicitly cast intel_region_id to intel_memory_type in
>> misaligned_pin
>> Reported-by: kernel test robot <lkp@intel.com>
>>
>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
>> ---
>> drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 128 ++++++++++++++++++
>> 1 file changed, 128 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> index b80788a2b7f9..f082b5ff3b5e 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
>> @@ -22,10 +22,12 @@
>> *
>> */
>> +#include "gt/intel_gtt.h"
>> #include <linux/list_sort.h>
>> #include <linux/prime_numbers.h>
>> #include "gem/i915_gem_context.h"
>> +#include "gem/i915_gem_region.h"
>> #include "gem/selftests/mock_context.h"
>> #include "gt/intel_context.h"
>> #include "gt/intel_gpu_commands.h"
>> @@ -1067,6 +1069,120 @@ static int shrink_boom(struct
>> i915_address_space *vm,
>> return err;
>> }
>> +static int misaligned_case(struct i915_address_space *vm, struct
>> intel_memory_region *mr,
>> + u64 addr, u64 size, unsigned long flags)
>> +{
>> + struct drm_i915_gem_object *obj;
>> + struct i915_vma *vma;
>> + int err = 0;
>> + u64 expected_vma_size, expected_node_size;
>> +
>> + obj = i915_gem_object_create_region(mr, size, 0, 0);
>> + if (IS_ERR(obj))
>> + return PTR_ERR(obj);
>> +
>> + vma = i915_vma_instance(obj, vm, NULL);
>> + if (IS_ERR(vma)) {
>> + err = PTR_ERR(vma);
>> + goto err_put;
>> + }
>> +
>> + err = i915_vma_pin(vma, 0, 0, addr | flags);
>> + if (err)
>> + goto err_put;
>> + i915_vma_unpin(vma);
>> +
>> + if (!drm_mm_node_allocated(&vma->node)) {
>> + err = -EINVAL;
>> + goto err_put;
>> + }
>> +
>> + if (i915_vma_misplaced(vma, 0, 0, addr | flags)) {
>> + err = -EINVAL;
>> + goto err_put;
>> + }
>> +
>> + expected_vma_size = round_up(size, 1 <<
>> (ffs(vma->resource->page_sizes_gtt) - 1));
>> + expected_node_size = expected_vma_size;
>> +
>> + if (IS_DG2(vm->i915) && i915_gem_object_is_lmem(obj)) {
>> + /* dg2 should expand lmem node to 2MB */
>
> Should this test be NEEDS_COMPACT_PT()?
>
> Otherwise LGTM. Reviewed-by: Thomas Hellström
> <thomas.hellstrom@linux.intel.com>
Thanks. Good catch, forgot to retrofit the new macro here.
>
>
next prev parent reply other threads:[~2022-01-26 17:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220125193530.3272386-1-bob.beckett@collabora.com>
2022-01-25 19:35 ` [PATCH v5 1/5] drm/i915: add needs_compact_pt flag Robert Beckett
2022-01-26 13:49 ` [Intel-gfx] " Thomas Hellström (Intel)
2022-01-26 17:11 ` Robert Beckett
2022-01-27 9:37 ` Thomas Hellström (Intel)
2022-01-31 14:19 ` Robert Beckett
2022-01-31 14:58 ` Thomas Hellström
2022-01-25 19:35 ` [PATCH v5 2/5] drm/i915: enforce min GTT alignment for discrete cards Robert Beckett
2022-01-26 15:45 ` [Intel-gfx] " Thomas Hellström (Intel)
2022-01-26 17:21 ` Robert Beckett
2022-01-25 19:35 ` [PATCH v5 3/5] drm/i915: support 64K GTT pages " Robert Beckett
2022-01-31 11:19 ` [Intel-gfx] " Thomas Hellström
2022-01-25 19:35 ` [PATCH v5 4/5] drm/i915: add gtt misalignment test Robert Beckett
2022-01-26 14:05 ` [Intel-gfx] " Thomas Hellström (Intel)
2022-01-26 17:22 ` Robert Beckett [this message]
2022-01-25 19:35 ` [PATCH v5 5/5] drm/i915/uapi: document behaviour for DG2 64K support Robert Beckett
2022-01-26 14:11 ` [Intel-gfx] " Thomas Hellström (Intel)
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