Re: [Intel-gfx] [PATCH v5 2/5] drm/i915: enforce min GTT alignment for discrete cards

[Robert Beckett <bob.beckett@collabora.com>]

On 26/01/2022 15:45, Thomas Hellström (Intel) wrote:
> 
> On 1/25/22 20:35, Robert Beckett wrote:
>> From: Matthew Auld <matthew.auld@intel.com>
>>
>> For local-memory objects we need to align the GTT addresses
>> to 64K, both for the ppgtt and ggtt.
>>
>> We need to support vm->min_alignment > 4K, depending
>> on the vm itself and the type of object we are inserting.
>> With this in mind update the GTT selftests to take this
>> into account.
>>
>> For compact-pt we further align and pad lmem object GTT addresses
>> to 2MB to ensure PDEs contain consistent page sizes as
>> required by the HW.
>>
>> v3:
>>     * use needs_compact_pt flag to discriminate between
>>       64K and 64K with compact-pt
>>     * add i915_vm_obj_min_alignment
>>     * use i915_vm_obj_min_alignment to round up vma reservation
>>       if compact-pt instead of hard coding
>> v5:
>>     * fix i915_vm_obj_min_alignment for internal objects which
>>       have no memory region
>>
>> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
>> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>   .../i915/gem/selftests/i915_gem_client_blt.c  | 23 +++--
>>   drivers/gpu/drm/i915/gt/intel_gtt.c           | 12 +++
>>   drivers/gpu/drm/i915/gt/intel_gtt.h           | 18 ++++
>>   drivers/gpu/drm/i915/i915_vma.c               |  9 ++
>>   drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 96 ++++++++++++-------
>>   5 files changed, 117 insertions(+), 41 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c 
>> b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> index c8ff8bf0986d..f0bfce53258f 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> @@ -39,6 +39,7 @@ struct tiled_blits {
>>       struct blit_buffer scratch;
>>       struct i915_vma *batch;
>>       u64 hole;
>> +    u64 align;
>>       u32 width;
>>       u32 height;
>>   };
>> @@ -410,14 +411,21 @@ tiled_blits_create(struct intel_engine_cs 
>> *engine, struct rnd_state *prng)
>>           goto err_free;
>>       }
>> -    hole_size = 2 * PAGE_ALIGN(WIDTH * HEIGHT * 4);
>> +    t->align = I915_GTT_PAGE_SIZE_2M; /* XXX worst case, derive from 
>> vm! */
>> +    t->align = max(t->align,
>> +               i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_LOCAL));
>> +    t->align = max(t->align,
>> +               i915_vm_min_alignment(t->ce->vm, INTEL_MEMORY_SYSTEM));
> 
> Don't we always end up with 2M here, regardless of the vm restrictions?
agreed. I will drop the 2M worst case.
> 
>