Re: [PATCH 2/2] mmc: sdhci-pci-gli: GL9767: Fix initializing the UHS-II interface during a power-on

[Adrian Hunter <adrian.hunter@intel.com>]

On 02/09/2025 10:12, Ben Chuang wrote:
> On Tue, Sep 2, 2025 at 2:33 PM Ben Chuang <benchuanggli@gmail.com> wrote:
>>
>> On Tue, Sep 2, 2025 at 1:02 AM Adrian Hunter <adrian.hunter@intel.com> wrote:
>>>
>>> On 01/09/2025 12:42, Ben Chuang wrote:
>>>> From: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>>>>
>>>> According to the power structure of IC hardware design for UHS-II
>>>> interface, reset control and timing must be added to the initialization
>>>> process of powering on the UHS-II interface.
>>>>
>>>> Fixes: 27dd3b82557a ("mmc: sdhci-pci-gli: enable UHS-II mode for GL9767")
>>>> Cc: stable@vger.kernel.org # v6.13+
>>>> Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
>>>> ---
>>>>  drivers/mmc/host/sdhci-pci-gli.c | 71 +++++++++++++++++++++++++++++++-
>>>>  1 file changed, 70 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
>>>> index 3a1de477e9af..85d0d7e6169c 100644
>>>> --- a/drivers/mmc/host/sdhci-pci-gli.c
>>>> +++ b/drivers/mmc/host/sdhci-pci-gli.c
>>>> @@ -283,6 +283,8 @@
>>>>  #define   PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE     0xb
>>>>  #define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL       BIT(6)
>>>>  #define   PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE         0x1
>>>> +#define   PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN   BIT(13)
>>>> +#define   PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE BIT(14)
>>>>
>>>>  #define GLI_MAX_TUNING_LOOP 40
>>>>
>>>> @@ -1179,6 +1181,69 @@ static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)
>>>>       gl9767_vhs_read(pdev);
>>>>  }
>>>>
>>>> +static void sdhci_gl9767_uhs2_phy_reset_assert(struct sdhci_host *host)
>>>> +{
>>>> +     struct sdhci_pci_slot *slot = sdhci_priv(host);
>>>> +     struct pci_dev *pdev = slot->chip->pdev;
>>>> +     u32 value;
>>>> +
>>>> +     gl9767_vhs_write(pdev);
>>>> +     pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
>>>> +     value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
>>>> +     pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>> +     value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
>>>> +     pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>> +     gl9767_vhs_read(pdev);
>>>> +}
>>>> +
>>>> +static void sdhci_gl9767_uhs2_phy_reset_deassert(struct sdhci_host *host)
>>>> +{
>>>> +     struct sdhci_pci_slot *slot = sdhci_priv(host);
>>>> +     struct pci_dev *pdev = slot->chip->pdev;
>>>> +     u32 value;
>>>> +
>>>> +     gl9767_vhs_write(pdev);
>>>> +     pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
>>>> +     value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
>>>
>>> Maybe add a small comment about PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE
>>> and PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN being updated separately.
>>>
>>>> +     pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>> +     value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
>>>> +     pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>> +     gl9767_vhs_read(pdev);
>>>> +}
>>>
>>> sdhci_gl9767_uhs2_phy_reset_assert() and sdhci_gl9767_uhs2_phy_reset_deassert()
>>> are fairly similar.  Maybe consider:
>>>
>>> static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert)
>>> {
>>>         struct sdhci_pci_slot *slot = sdhci_priv(host);
>>>         struct pci_dev *pdev = slot->chip->pdev;
>>>         u32 value, set, clr;
>>>
>>>         if (assert) {
>>>                 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
>>>                 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
>>>         } else {
>>>                 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
>>>                 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
>>>         }
>>>
>>>         gl9767_vhs_write(pdev);
>>>         pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
>>>         value |= set;
>>>         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>         value &= ~clr;
>>>         pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
>>>         gl9767_vhs_read(pdev);
>>> }
>>>
>>
>> OK, I will update it. Thank you.
>>
>>>
>>>> +
>>>> +static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)
>>>> +{
>>>> +     u8 pwr = 0;
>>>> +
>>>> +     if (mode != MMC_POWER_OFF) {
>>>> +             pwr = sdhci_get_vdd_value(vdd);
>>>> +             if (!pwr)
>>>> +                     WARN(1, "%s: Invalid vdd %#x\n",
>>>> +                          mmc_hostname(host->mmc), vdd);
>>>> +             pwr |= SDHCI_VDD2_POWER_180;
>>>> +     }
>>>> +
>>>> +     if (host->pwr == pwr)
>>>> +             return;
>>>> +
>>>> +     host->pwr = pwr;
>>>> +
>>>> +     if (pwr == 0) {
>>>> +             sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
>>>> +     } else {
>>>> +             sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
>>>> +
>>>> +             pwr |= SDHCI_POWER_ON;
>>>> +             sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);
>>>> +             mdelay(5);
>>>
>>> Can be mmc_delay(5)
>>>
>>>> +
>>>> +             sdhci_gl9767_uhs2_phy_reset_assert(host);
>>>> +             pwr |= SDHCI_VDD2_POWER_ON;
>>>> +             sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
>>>> +             mdelay(5);
>>>
>>> Can be mmc_delay(5)
>>
>> I may not modify it now.
>> mmc_delay() is in "drivers/mmc/core/core.h".
>> If sdhci-pci-gli.c only includes "../core/core.h", the compiler will
>> report some errors.
> 
> Ah, just add another headersand it will build.
> 
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -14,6 +14,8 @@
>  #include <linux/delay.h>
>  #include <linux/of.h>
>  #include <linux/iopoll.h>
> +#include <linux/mmc/host.h>
> +#include "../core/core.h"
>  #include "sdhci.h"
>  #include "sdhci-cqhci.h"
>  #include "sdhci-pci.h"
> @@ -968,10 +970,10 @@ static void gl9755_set_power(struct sdhci_host
> *host, unsigned char mode,
> 
>                 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);
>                 /* wait stable */
> -               mdelay(5);
> +               mmc_delay(5);
>                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
>                 /* wait stable */
> -               mdelay(5);
> +               mmc_delay(5);
>                 sdhci_gli_overcurrent_event_enable(host, true);
>         }

It seems mmc_delay() is for core mmc code only, not host drivers.
But the issue with mdelay is that it does not sleep.  Other options
are msleep() or usleep_range().