[PATCH 0/3] clk: bcm2835: describe the BCM2711 GISB clock for the GENET MDIO controller

[PATCH 0/3] clk: bcm2835: describe the BCM2711 GISB clock for the GENET MDIO controller

[Nicolai Buchwitz]

The timestamped MDIO write series [1] needs the reference clock the
GENET MDIO controller divides its MDC from. On BCM2711 that clock is
not described anywhere, so 5/5 of that series hardcodes 200 MHz behind
a compatible match, and mdio-bcm-unimac's clock-frequency handling
assumes the 250 MHz of the STB chips.

On BCM2711 the MDC is derived from the CPRMAN generator at 0x1d8, which
the firmware calls gisb and has always run at 200 MHz (PLLD_PER 750 MHz
/ 3.75). Changing that divider at runtime moves the MDIO busy time by
the same ratio, see [2], and Phil confirmed it from the
Raspberry Pi side. GISB is the register bus of the STB peripherals,
which is where the driver's 250 MHz default comes from.

This adds a clock id, the generator in clk-bcm2835 (critical, the
firmware enables it and nothing in Linux owns it) and a clocks property
on the mdio node, like Stefan did for EMMC2.

No functional change by itself. The driver only looks the clock up
with [1], and only for the timestamp bounds. Making
unimac_mdio_clk_set() use the real rate is a follow-up, as that moves
the Pi 400, whose clock-frequency = <1950000> currently lands at
1.56 MHz instead of 1.95. The limit is a level shifter on that board,
so the follow-up keeps it at 1.56 MHz.

Patches 1 and 2 are for the clk tree, patch 3 for Florian once the
header is in. dtbs_check clean, booted on a CM4: clk_summary shows
gisb at 200 MHz under plld_per, eth0 comes up as before.

[1] https://lore.kernel.org/netdev/20261009143506.2507607-1-jjc@jclark.com/
[2] https://lore.kernel.org/netdev/60accbd89cfaf0d4be1da5ec2fafd975@tipi-net.de/

---
Nicolai Buchwitz (3):
      dt-bindings: clock: bcm2835: add the BCM2711 GISB clock
      clk: bcm2835: register the BCM2711 GISB clock
      ARM: dts: bcm2711: give the GENET MDIO controller its clock

 arch/arm/boot/dts/broadcom/bcm2711.dtsi |  1 +
 drivers/clk/bcm/clk-bcm2835.c           | 16 ++++++++++++++++
 include/dt-bindings/clock/bcm2835.h     |  1 +
 3 files changed, 18 insertions(+)
---
base-commit: 72d3fcf802c45d00b300f25b848a93c3a2bd7c7e
change-id: 20261012-devel-bcm2711-gisb-clk-cf8eea19c46a

Best regards,
--  
Nicolai Buchwitz <nb@tipi-net.de>

[PATCH 1/3] dt-bindings: clock: bcm2835: add the BCM2711 GISB clock

[Nicolai Buchwitz]

BCM2711 has a clock generator for the GISB bus that the firmware sets
up at 200 MHz. The GENET MDIO controller runs its MDC off it, so add an
id for it.

Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>
---
 include/dt-bindings/clock/bcm2835.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/dt-bindings/clock/bcm2835.h b/include/dt-bindings/clock/bcm2835.h
index b60c03430cf15..3186da543f975 100644
--- a/include/dt-bindings/clock/bcm2835.h
+++ b/include/dt-bindings/clock/bcm2835.h
@@ -60,3 +60,4 @@
 #define BCM2835_CLOCK_DSI1P		50
 
 #define BCM2711_CLOCK_EMMC2		51
+#define BCM2711_CLOCK_GISB		52

-- 
2.53.0

[PATCH 2/3] clk: bcm2835: register the BCM2711 GISB clock

[Nicolai Buchwitz]

The generator at CM offset 0x1d8 is not in any documentation I could
find, but the firmware calls it gisb and runs it at 200 MHz off
PLLD_PER with a 3.75 divider. GISB is the register bus of the STB
peripherals, and on BCM2711 the GENET MDIO controller clocks its MDC
from it. mdio-bcm-unimac wants that rate to work out the MDC period.

Mark it critical. The firmware enables it at boot and nothing in Linux
owns it, so it must never be gated.

Checked on a Raspberry Pi CM4 by moving the divider at runtime, the
MDIO busy time follows it.

Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>
---
 drivers/clk/bcm/clk-bcm2835.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 118df86d717c6..bc1de20c7e00e 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -117,6 +117,8 @@
 #define CM_EMMCDIV		0x1c4
 #define CM_EMMC2CTL		0x1d0
 #define CM_EMMC2DIV		0x1d4
+#define CM_GISBCTL		0x1d8
+#define CM_GISBDIV		0x1dc
 
 /* General bits for the CM_*CTL regs */
 # define CM_ENABLE			BIT(4)
@@ -2097,6 +2099,20 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
 		.frac_bits = 8,
 		.tcnt_mux = 42),
 
+	/*
+	 * GISB clock (only available for BCM2711): the STB peripheral
+	 * register bus, set up by the firmware. The GENET MDIO controller
+	 * derives its MDC from it.
+	 */
+	[BCM2711_CLOCK_GISB]	= REGISTER_PER_CLK(
+		SOC_BCM2711,
+		.name = "gisb",
+		.ctl_reg = CM_GISBCTL,
+		.div_reg = CM_GISBDIV,
+		.int_bits = 4,
+		.frac_bits = 8,
+		.flags = CLK_IS_CRITICAL),
+
 	/* General purpose (GPIO) clocks */
 	[BCM2835_CLOCK_GP0]	= REGISTER_PER_CLK(
 		SOC_ALL,

-- 
2.53.0

[PATCH 3/3] ARM: dts: bcm2711: give the GENET MDIO controller its clock

[Nicolai Buchwitz]

The MDC of the GENET MDIO controller comes from the GISB clock.
Describe it, so mdio-bcm-unimac can get the real 200 MHz from
clk_get_rate() instead of assuming the 250 MHz of the STB chips, and
can put bounds on when an MDIO write completes for PTP.

Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>
---
 arch/arm/boot/dts/broadcom/bcm2711.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm2711.dtsi b/arch/arm/boot/dts/broadcom/bcm2711.dtsi
index 5e3b4bb393967..82b38551d55cf 100644
--- a/arch/arm/boot/dts/broadcom/bcm2711.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm2711.dtsi
@@ -597,6 +597,7 @@ genet_mdio: mdio@e14 {
 				compatible = "brcm,genet-mdio-v5";
 				reg = <0xe14 0x8>;
 				reg-names = "mdio";
+				clocks = <&clocks BCM2711_CLOCK_GISB>;
 				#address-cells = <0x1>;
 				#size-cells = <0x0>;
 			};

-- 
2.53.0

Re: [PATCH 1/3] dt-bindings: clock: bcm2835: add the BCM2711 GISB clock

[Florian Fainelli]

On 10/20/26 07:58, Nicolai Buchwitz wrote:
> BCM2711 has a clock generator for the GISB bus that the firmware sets
> up at 200 MHz. The GENET MDIO controller runs its MDC off it, so add an
> id for it.
> 
> Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [PATCH 3/3] ARM: dts: bcm2711: give the GENET MDIO controller its clock

[Florian Fainelli]

On 10/20/26 07:58, Nicolai Buchwitz wrote:
> The MDC of the GENET MDIO controller comes from the GISB clock.
> Describe it, so mdio-bcm-unimac can get the real 200 MHz from
> clk_get_rate() instead of assuming the 250 MHz of the STB chips, and
> can put bounds on when an MDIO write completes for PTP.
> 
> Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
-- 
Florian

Re: [PATCH 2/3] clk: bcm2835: register the BCM2711 GISB clock

[Florian Fainelli]

On 10/20/26 07:58, Nicolai Buchwitz wrote:
> The generator at CM offset 0x1d8 is not in any documentation I could
> find, but the firmware calls it gisb and runs it at 200 MHz off
> PLLD_PER with a 3.75 divider. GISB is the register bus of the STB
> peripherals, and on BCM2711 the GENET MDIO controller clocks its MDC
> from it. mdio-bcm-unimac wants that rate to work out the MDC period.
> 
> Mark it critical. The firmware enables it at boot and nothing in Linux
> owns it, so it must never be gated.
> 
> Checked on a Raspberry Pi CM4 by moving the divider at runtime, the
> MDIO busy time follows it.
> 
> Signed-off-by: Nicolai Buchwitz <nb@tipi-net.de>

Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>

> ---
>   drivers/clk/bcm/clk-bcm2835.c | 16 ++++++++++++++++
>   1 file changed, 16 insertions(+)
> 
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 118df86d717c6..bc1de20c7e00e 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -117,6 +117,8 @@
>   #define CM_EMMCDIV		0x1c4
>   #define CM_EMMC2CTL		0x1d0
>   #define CM_EMMC2DIV		0x1d4
> +#define CM_GISBCTL		0x1d8
> +#define CM_GISBDIV		0x1dc

Yes, those names are correct and accurate here.
-- 
Florian