From: <Ryan.Wanner@microchip.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>,
<nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<claudiu.beznea@tuxon.dev>
Cc: <robh@kernel.org>, <linux-clk@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<varshini.rajendran@microchip.com>
Subject: [PATCH v2 22/32] clk: at91: sama5d3: switch to parent_hw and parent_data
Date: Tue, 24 Jun 2025 08:08:19 -0700 [thread overview]
Message-ID: <61c9978f367ee3dbc3fb45bc5502ca5729f735d0.1750182562.git.Ryan.Wanner@microchip.com> (raw)
In-Reply-To: <cover.1750182562.git.Ryan.Wanner@microchip.com>
From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Switch SAMA5D3 clocks to use parent_hw and parent_data. Having
parent_hw instead of parent names improves to clock registration
speed and re-parenting.
Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
drivers/clk/at91/sama5d3.c | 122 +++++++++++++++++++------------------
1 file changed, 63 insertions(+), 59 deletions(-)
diff --git a/drivers/clk/at91/sama5d3.c b/drivers/clk/at91/sama5d3.c
index 05d0cdd22bc4..e5b061783b09 100644
--- a/drivers/clk/at91/sama5d3.c
+++ b/drivers/clk/at91/sama5d3.c
@@ -37,9 +37,9 @@ static const struct clk_pcr_layout sama5d3_pcr_layout = {
.div_mask = GENMASK(17, 16),
};
-static const struct {
+static struct {
char *n;
- char *p;
+ struct clk_hw *parent_hw;
unsigned long flags;
u8 id;
} sama5d3_systemck[] = {
@@ -47,14 +47,14 @@ static const struct {
* ddrck feeds DDR controller and is enabled by bootloader thus we need
* to keep it enabled in case there is no Linux consumer for it.
*/
- { .n = "ddrck", .p = "masterck_div", .id = 2, .flags = CLK_IS_CRITICAL },
- { .n = "lcdck", .p = "masterck_div", .id = 3 },
- { .n = "smdck", .p = "smdclk", .id = 4 },
- { .n = "uhpck", .p = "usbck", .id = 6 },
- { .n = "udpck", .p = "usbck", .id = 7 },
- { .n = "pck0", .p = "prog0", .id = 8 },
- { .n = "pck1", .p = "prog1", .id = 9 },
- { .n = "pck2", .p = "prog2", .id = 10 },
+ { .n = "ddrck", .id = 2, .flags = CLK_IS_CRITICAL },
+ { .n = "lcdck", .id = 3 },
+ { .n = "smdck", .id = 4 },
+ { .n = "uhpck", .id = 6 },
+ { .n = "udpck", .id = 7 },
+ { .n = "pck0", .id = 8 },
+ { .n = "pck1", .id = 9 },
+ { .n = "pck2", .id = 10 },
};
static const struct {
@@ -114,24 +114,15 @@ static const struct {
static void __init sama5d3_pmc_setup(struct device_node *np)
{
- const char *slck_name, *mainxtal_name;
+ const char *slow_clk_name = "slowck", *main_xtal_name = "main_xtal";
+ struct clk_hw *main_rc_hw, *main_osc_hw, *mainck_hw;
+ u8 slow_clk_index = 0, main_xtal_index = 1;
+ struct clk_hw *smdck_hw, *usbck_hw, *hw;
+ struct clk_parent_data parent_data[5];
struct pmc_data *sama5d3_pmc;
- const char *parent_names[5];
struct regmap *regmap;
- struct clk_hw *hw;
- int i;
bool bypass;
-
- i = of_property_match_string(np, "clock-names", "slow_clk");
- if (i < 0)
- return;
-
- slck_name = of_clk_get_parent_name(np, i);
-
- i = of_property_match_string(np, "clock-names", "main_xtal");
- if (i < 0)
- return;
- mainxtal_name = of_clk_get_parent_name(np, i);
+ int i;
regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
@@ -143,54 +134,55 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
if (!sama5d3_pmc)
return;
- hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
- 50000000);
- if (IS_ERR(hw))
+ main_rc_hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
+ 50000000);
+ if (IS_ERR(main_rc_hw))
goto err_free;
bypass = of_property_read_bool(np, "atmel,osc-bypass");
- hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name, NULL,
- bypass);
- if (IS_ERR(hw))
+ main_osc_hw = at91_clk_register_main_osc(regmap, "main_osc", NULL,
+ &AT91_CLK_PD_NAME(main_xtal_name, main_xtal_index),
+ bypass);
+ if (IS_ERR(main_osc_hw))
goto err_free;
- parent_names[0] = "main_rc_osc";
- parent_names[1] = "main_osc";
- hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, NULL, 2);
- if (IS_ERR(hw))
+ parent_data[0] = AT91_CLK_PD_HW(main_rc_hw);
+ parent_data[1] = AT91_CLK_PD_HW(main_osc_hw);
+ mainck_hw = at91_clk_register_sam9x5_main(regmap, "mainck", NULL, parent_data, 2);
+ if (IS_ERR(mainck_hw))
goto err_free;
- hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
+ hw = at91_clk_register_pll(regmap, "pllack", NULL, &AT91_CLK_PD_HW(mainck_hw), 0,
&sama5d3_pll_layout, &plla_characteristics);
if (IS_ERR(hw))
goto err_free;
- hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
+ hw = at91_clk_register_plldiv(regmap, "plladivck", NULL, &AT91_CLK_PD_HW(hw));
if (IS_ERR(hw))
goto err_free;
sama5d3_pmc->chws[PMC_PLLACK] = hw;
- hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck", NULL);
+ hw = at91_clk_register_utmi(regmap, NULL, "utmick", NULL, &AT91_CLK_PD_HW(mainck_hw));
if (IS_ERR(hw))
goto err_free;
sama5d3_pmc->chws[PMC_UTMI] = hw;
- parent_names[0] = slck_name;
- parent_names[1] = "mainck";
- parent_names[2] = "plladivck";
- parent_names[3] = "utmick";
+ parent_data[0] = AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index);
+ parent_data[1] = AT91_CLK_PD_HW(mainck_hw);
+ parent_data[2] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]);
+ parent_data[3] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]);
hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
- parent_names, NULL,
+ NULL, parent_data,
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock);
if (IS_ERR(hw))
goto err_free;
hw = at91_clk_register_master_div(regmap, "masterck_div",
- "masterck_pres", NULL,
+ NULL, &AT91_CLK_PD_HW(hw),
&at91sam9x5_master_layout,
&mck_characteristics, &mck_lock,
CLK_SET_RATE_GATE, 0);
@@ -199,28 +191,30 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
sama5d3_pmc->chws[PMC_MCK] = hw;
- parent_names[0] = "plladivck";
- parent_names[1] = "utmick";
- hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, NULL, 2);
- if (IS_ERR(hw))
+ parent_data[0] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]);
+ parent_data[1] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]);
+ usbck_hw = at91sam9x5_clk_register_usb(regmap, "usbck", NULL, parent_data, 2);
+ if (IS_ERR(usbck_hw))
goto err_free;
- hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
- if (IS_ERR(hw))
+ parent_data[0] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]);
+ parent_data[1] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]);
+ smdck_hw = at91sam9x5_clk_register_smd(regmap, "smdclk", NULL, parent_data, 2);
+ if (IS_ERR(smdck_hw))
goto err_free;
- parent_names[0] = slck_name;
- parent_names[1] = "mainck";
- parent_names[2] = "plladivck";
- parent_names[3] = "utmick";
- parent_names[4] = "masterck_div";
+ parent_data[0] = AT91_CLK_PD_NAME(slow_clk_name, slow_clk_index);
+ parent_data[1] = AT91_CLK_PD_HW(mainck_hw);
+ parent_data[2] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_PLLACK]);
+ parent_data[3] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_UTMI]);
+ parent_data[4] = AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]);
for (i = 0; i < 3; i++) {
char name[6];
snprintf(name, sizeof(name), "prog%d", i);
hw = at91_clk_register_programmable(regmap, name,
- parent_names, NULL, 5, i,
+ NULL, parent_data, 5, i,
&at91sam9x5_programmable_layout,
NULL);
if (IS_ERR(hw))
@@ -229,9 +223,18 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
sama5d3_pmc->pchws[i] = hw;
}
+ /* Set systemck parent hws. */
+ sama5d3_systemck[0].parent_hw = sama5d3_pmc->chws[PMC_MCK];
+ sama5d3_systemck[1].parent_hw = sama5d3_pmc->chws[PMC_MCK];
+ sama5d3_systemck[2].parent_hw = smdck_hw;
+ sama5d3_systemck[3].parent_hw = usbck_hw;
+ sama5d3_systemck[4].parent_hw = usbck_hw;
+ sama5d3_systemck[5].parent_hw = sama5d3_pmc->pchws[0];
+ sama5d3_systemck[6].parent_hw = sama5d3_pmc->pchws[1];
+ sama5d3_systemck[7].parent_hw = sama5d3_pmc->pchws[2];
for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) {
- hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n,
- sama5d3_systemck[i].p, NULL,
+ hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n, NULL,
+ &AT91_CLK_PD_HW(sama5d3_systemck[i].parent_hw),
sama5d3_systemck[i].id,
sama5d3_systemck[i].flags);
if (IS_ERR(hw))
@@ -244,7 +247,8 @@ static void __init sama5d3_pmc_setup(struct device_node *np)
hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
&sama5d3_pcr_layout,
sama5d3_periphck[i].n,
- "masterck_div", NULL,
+ NULL,
+ &AT91_CLK_PD_HW(sama5d3_pmc->chws[PMC_MCK]),
sama5d3_periphck[i].id,
&sama5d3_periphck[i].r,
INT_MIN,
--
2.43.0
next prev parent reply other threads:[~2025-06-24 15:09 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 15:07 [PATCH v2 00/32] clk: at91: add support for parent_data and Ryan.Wanner
2025-06-24 15:07 ` [PATCH v2 01/32] clk: at91: pmc: add macros for clk_parent_data Ryan.Wanner
2025-06-24 15:07 ` [PATCH v2 02/32] clk: at91: pmc: Move macro to header file Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 03/32] clk: at91: clk-sam9x60-pll: use clk_parent_data Ryan.Wanner
2025-07-07 13:21 ` Claudiu Beznea
2025-07-07 15:24 ` Ryan Wanner
2025-07-08 10:05 ` Claudiu Beznea
2025-06-24 15:08 ` [PATCH v2 04/32] clk: at91: clk-peripheral: switch to clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 05/32] clk: at91: clk-main: switch to clk parent data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 06/32] clk: at91: clk-utmi: use clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 07/32] clk: at91: clk-master: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 08/32] clk: at91: clk-programmable: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 09/32] clk: at91: clk-generated: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 10/32] clk: at91: clk-usb: add support for clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 11/32] clk: at91: clk-system: use clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 12/32] clk: at91: clk-pll: add support for parent_hw Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 13/32] clk: at91: clk-audio-pll: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 14/32] clk: at91: clk-plldiv: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 15/32] clk: at91: clk-h32mx: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 16/32] clk: at91: clk-i2s-mux: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 17/32] clk: at91: clk-smd: add support for clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 18/32] clk: at91: clk-slow: add support for parent_hw Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 19/32] clk: at91: dt-compat: switch to parent_hw and parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 20/32] clk: at91: sam9x60: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 21/32] clk: at91: sama5d2: " Ryan.Wanner
2025-07-07 13:21 ` Claudiu Beznea
2025-06-24 15:08 ` Ryan.Wanner [this message]
2025-06-24 15:08 ` [PATCH v2 23/32] clk: at91: sama5d4: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 24/32] clk: at91: at91sam9x5: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 25/32] clk: at91: at91rm9200: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 26/32] clk: at91: at91sam9260: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 27/32] clk: at91: at91sam9g45: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 28/32] clk: at91: at91sam9n12: " Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 29/32] clk: at91: at91sam9rl: switch to clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 30/32] clk: at91: sam9x75: switch to parent_hw and parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 31/32] clk: at91: sama7g5: switch to clk_parent_data Ryan.Wanner
2025-06-24 15:08 ` [PATCH v2 32/32] clk: at91: sama7d65: " Ryan.Wanner
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