Re: [RFC PATCH V2 0/1] x86: cpu topology fix and question on x86_max_cores

["Zhang, Rui" <rui.zhang@intel.com>]

> > > 
> > I thought of improving this by parsing all the valid APIC-IDs in
> > MADT
> > during BSP bootup, and get such information by decoding the APIC-
> > IDs
> > using the APIC-ID layout information retrieved from BSP. But this
> > is
> > likely to be a fertile new source of bugs as Dave concerned.
> 
> The APIC-IDs are only usefull if there is an architected scheme how
> they
> are assigned. Is there such a thing?

I don't know.
Do you think it helps if the APIC-ID layout are defined to be identical
across all CPUs?
In this case, BSP knows the APIC-ID layout of itself and this can apply
to the other APIC-IDs.

> 
> The SDM is not helpful at all, but according to the ACPI spec there
> exists:
> 
>   Processor Properties Topology Table (PPTT)
> 
> That table actually provides pretty much what we are looking for, but
> that table is optional and there is actually code for that in the
> kernel, which is ARM64 specific.
> 
> So while this would be useful it's not usable on x86 because that
> would
> make too much sense, right?

Thanks for pointing to this.

I got a brief view of PPTT. So far, my understanding is that PPTT
provides
1. the cpu Hierarchy, but package level only. There may be multiple
levels but it does not tell us if it is a Die, Module or Core.
2. the cache Hierarchy

I need to find one real PPTT implementation to see how it works.

thanks,
rui