From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, ziyue.zhang@oss.qualcomm.com,
krishna.chundru@oss.qualcomm.com
Subject: Re: [PATCH] arm64: dts: qcom: monaco-evk: Enable PCIe0 and PCIe1 on monaco-evk
Date: Wed, 12 Nov 2025 10:15:39 +0100 [thread overview]
Message-ID: <66b634ef-6a69-4275-b28d-2b148df22b24@oss.qualcomm.com> (raw)
In-Reply-To: <20251111-monaco-evk-pci-v1-1-8013d0d6a7ca@quicinc.com>
On 11/11/25 11:08 AM, Sushrut Shree Trivedi wrote:
> Enables PCIe0 and PCIe1 controller and phy-nodes.
>
> PCIe0 is routed to an m.2 E key connector on the mainboard for wifi
> attaches while PCIe1 routes to a standard PCIe x4 expansion slot.
>
> Signed-off-by: Sushrut Shree Trivedi <quic_sushruts@quicinc.com>
> ---
> This patch depends on the series:
> https://lore.kernel.org/all/20251024095609.48096-1-ziyue.zhang@oss.qualcomm.com/
> ---
[...]
> + perst-pins {
> + pins = "gpio2";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
Neither of the two active-low reset pins should be pull-down, use
bias-disable to avoid spurious assertions
Konrad
prev parent reply other threads:[~2025-11-12 9:15 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-11 10:08 Sushrut Shree Trivedi
2025-11-11 15:47 ` Bjorn Andersson
2025-11-12 9:15 ` Konrad Dybcio [this message]
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