[GIT PULL] Compute Express Link (CXL) Fixes for 6.12-rc6

[GIT PULL] Compute Express Link (CXL) Fixes for 6.12-rc6

[Ira Weiny]

Linus, please pull from:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git tags/cxl-fixes-6.12-rc6

The bulk of these fixes center around an initialization order bug reported by
Gregory Price and some additional fall out from the debugging effort.

In summary, cxl_acpi and cxl_mem race and previously worked because of a
bus_rescan_devices() while testing without modules built in.  Unfortunately
with modules built in the rescan would fail due to the cxl_port driver being
registered late via the build order.  Furthermore it was found
bus_rescan_devices() did not guarantee a probe barrier which CXL was expecting.
Additional fixes to cxl-test and decoder allocation came along as they were
found in this debugging effort.

The other fixes are pretty minor but one affects trace point data seen by user
space.

Apologies in advance for the later PR.  These fixes just missed rc5 last week.
I did get them pushed to our fixes branch last Friday 10/25 but they only
appeared in linux-next on the 30th.  So I've waited a couple more days to send
the PR.


---

The following changes since commit 42f7652d3eb527d03665b09edac47f85fb600924:

  Linux 6.12-rc4 (2024-10-20 15:19:38 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git tags/cxl-fixes-6.12-rc6

for you to fetch changes up to 3a2b97b3210bd5758f66fad04c5171f85a016a04:

  cxl/test: Improve init-order fidelity relative to real-world systems (2024-10-25 16:07:04 -0500)

----------------------------------------------------------------
cxl fixes for v6.12-rc6

	- Fix crashes when running with cxl-test code
	- Fix Trace DRAM Event Record field decodes
	- Fix module/built in initialization order errors
	- Fix use after free on decoder shutdowns
	- Fix out of order decoder allocations
	- Improve cxl-test to better reflect real world systems

----------------------------------------------------------------
Dan Williams (6):
      cxl/port: Fix CXL port initialization order when the subsystem is built-in
      cxl/port: Fix cxl_bus_rescan() vs bus_rescan_devices()
      cxl/acpi: Ensure ports ready at cxl_acpi_probe() return
      cxl/port: Fix use-after-free, permit out-of-order decoder shutdown
      cxl/port: Prevent out-of-order decoder allocation
      cxl/test: Improve init-order fidelity relative to real-world systems

Li Zhijian (1):
      cxl/core: Return error when cxl_endpoint_gather_bandwidth() handles a non-PCI device

Shiju Jose (1):
      cxl/events: Fix Trace DRAM Event Record

 drivers/base/core.c          |  35 ++++++++
 drivers/cxl/Kconfig          |   1 +
 drivers/cxl/Makefile         |  20 +++--
 drivers/cxl/acpi.c           |   7 ++
 drivers/cxl/core/cdat.c      |   3 +
 drivers/cxl/core/hdm.c       |  50 +++++++++--
 drivers/cxl/core/port.c      |  13 ++-
 drivers/cxl/core/region.c    |  91 ++++++++++----------
 drivers/cxl/core/trace.h     |  17 +++-
 drivers/cxl/cxl.h            |   3 +-
 drivers/cxl/port.c           |  17 +++-
 include/linux/device.h       |   3 +
 tools/testing/cxl/test/cxl.c | 200 +++++++++++++++++++++++--------------------
 tools/testing/cxl/test/mem.c |   1 +
 14 files changed, 302 insertions(+), 159 deletions(-)

Re: [GIT PULL] Compute Express Link (CXL) Fixes for 6.12-rc6

[pr-tracker-bot]

The pull request you sent on Fri, 1 Nov 2024 13:49:54 -0500:

> git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git tags/cxl-fixes-6.12-rc6

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/b1966a1fd218e1f5d5376bf352f9a4c26aba50b5

Thank you!

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