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From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com,
	maz@kernel.org, suzuki.poulose@arm.com,
	James Morse <james.morse@arm.com>,
	kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes
Date: Wed, 29 Apr 2020 15:07:15 +0530	[thread overview]
Message-ID: <6749304e-8a4d-f4b9-eb40-91f0dd13166e@arm.com> (raw)
In-Reply-To: <1586857710-17154-1-git-send-email-anshuman.khandual@arm.com>



On 04/14/2020 03:18 PM, Anshuman Khandual wrote:
> This series is primarily motivated from an adhoc list from Mark Rutland
> during our previous ID_ISAR6 discussion [1]. The current proposal also
> accommodates some more suggestions from Will and Suzuki.
> 
> This series adds missing 32 bit system registers (ID_PFR2, ID_DFR1 and
> ID_MMFR5), adds missing features bits on all existing system registers
> (32 and 64 bit) and some other miscellaneous changes. While here it also
> includes a patch which does macro replacement for various open bits shift
> encodings for various CPU ID registers. There is a slight re-order of the
> patches here as compared to the previous version (V1).
> 
> This series is based on v5.7-rc1. All feature bits enabled here can be
> referred in ARM DDI 0487F.a specification. Though I have tried to select
> appropriate values for each new feature being added here, there might be
> some inconsistencies (or mistakes). In which case, please do let me know
> if anything needs to change. Thank you.
> 
> [1] https://patchwork.kernel.org/patch/11287805/
> 
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com> 
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> 
> Changes in V2:
> 
> - Added Suggested-by tag from Mark Rutland for all changes he had proposed
> - Added comment for SpecSEI feature on why it is HIGHER_SAFE per Suzuki
> - Added a patch which makes ID_AA64DFR0_DOUBLELOCK a signed feature per Suzuki
> - Added ID_DFR1 and ID_MMFR5 system register definitions per Will
> - Added remaining features bits for relevant 64 bit system registers per Will
> - Changed commit message on [PATCH 5/7] regarding TraceFilt feature per Suzuki
> - Changed ID_PFR2.CSV3 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will
> - Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will 
> - Changed some commit messages

Hello Will,

Just a gentle ping. I am wondering if you had a chance to glance
through this updated series.

- Anshuman

  parent reply	other threads:[~2020-04-29  9:37 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-14  9:48 Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 01/16] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 02/16] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 03/16] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 05/16] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 06/16] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 07/16] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 08/16] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 09/16] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 10/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 11/16] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 12/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 13/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 14/16] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 15/16] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-04-14  9:48 ` [PATCH V2 16/16] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-04-29  9:37 ` Anshuman Khandual [this message]
2020-04-29 21:26   ` [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Will Deacon
2020-04-30  2:59     ` Anshuman Khandual
2020-04-30 16:47       ` Will Deacon

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