Re: [PATCH V2 00/16] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes

[Anshuman Khandual <anshuman.khandual@arm.com>]

On 04/30/2020 02:56 AM, Will Deacon wrote:
> Hi Anshuman,
> 
> On Wed, Apr 29, 2020 at 03:07:15PM +0530, Anshuman Khandual wrote:
>> On 04/14/2020 03:18 PM, Anshuman Khandual wrote:
>>> This series is primarily motivated from an adhoc list from Mark Rutland
>>> during our previous ID_ISAR6 discussion [1]. The current proposal also
>>> accommodates some more suggestions from Will and Suzuki.
>>>
>>> This series adds missing 32 bit system registers (ID_PFR2, ID_DFR1 and
>>> ID_MMFR5), adds missing features bits on all existing system registers
>>> (32 and 64 bit) and some other miscellaneous changes. While here it also
>>> includes a patch which does macro replacement for various open bits shift
>>> encodings for various CPU ID registers. There is a slight re-order of the
>>> patches here as compared to the previous version (V1).
>>>
>>> This series is based on v5.7-rc1. All feature bits enabled here can be
>>> referred in ARM DDI 0487F.a specification. Though I have tried to select
>>> appropriate values for each new feature being added here, there might be
>>> some inconsistencies (or mistakes). In which case, please do let me know
>>> if anything needs to change. Thank you.
>>>
>>> [1] https://patchwork.kernel.org/patch/11287805/
>>>
>>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>>> Cc: Will Deacon <will@kernel.org>
>>> Cc: Mark Rutland <mark.rutland@arm.com> 
>>> Cc: Marc Zyngier <maz@kernel.org>
>>> Cc: James Morse <james.morse@arm.com>
>>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> Cc: kvmarm@lists.cs.columbia.edu
>>> Cc: linux-arm-kernel@lists.infradead.org
>>> Cc: linux-kernel@vger.kernel.org
>>>
>>> Changes in V2:
>>>
>>> - Added Suggested-by tag from Mark Rutland for all changes he had proposed
>>> - Added comment for SpecSEI feature on why it is HIGHER_SAFE per Suzuki
>>> - Added a patch which makes ID_AA64DFR0_DOUBLELOCK a signed feature per Suzuki
>>> - Added ID_DFR1 and ID_MMFR5 system register definitions per Will
>>> - Added remaining features bits for relevant 64 bit system registers per Will
>>> - Changed commit message on [PATCH 5/7] regarding TraceFilt feature per Suzuki
>>> - Changed ID_PFR2.CSV3 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will
>>> - Changed ID_PFR0.CSV2 (FTR_STRICT -> FTR_NONSTRICT) as 64 bit registers per Will 
>>> - Changed some commit messages
>>
>> Just a gentle ping. I am wondering if you had a chance to glance
>> through this updated series.
> 
> Please can you resend based on for-next/cpufeature?

Sure, will do.