From: "Chang S. Bae" <chang.seok.bae@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
<tglx@kernel.org>, <mingo@redhat.com>,
<dave.hansen@linux.intel.com>, <kevin.shu@intel.com>
Subject: Re: [PATCH RFC v1 1/8] cpu/hotplug: Allow architecture-specific primary CPU bringup
Date: Tue, 29 Sep 2026 21:44:55 -0700 [thread overview]
Message-ID: <67b77f20-53f1-4b3c-8420-f125eaa0fe26@intel.com> (raw)
In-Reply-To: <20260930002010.GDarxVul0JZDam_-bG@fat_crate.local>
On 9/29/2026 5:20 PM, Borislav Petkov wrote:
> On Sat, Sep 12, 2026 at 12:08:07AM +0000, Chang S. Bae wrote:
>> Parallel CPU bringup currently proceeds in two phases: first for the SMT
>> primary threads and then second for the remaining secondary threads. This
>> ordering avoids race conditions, specifically for x86 microcode loading.
>>
>> Upcoming x86 changes expand the microcode loading scope beyond a single
>> core to package scope or even system-wide updates. Introduce architecture
>> hooks that allow customizing which CPUs participate in the first phase:
>>
>> * arch_cpuhp_primary_aware() - indicates whether the architecture
>> provides a custom primary CPU selection scheme, or not.
>>
>> * arch_cpuhp_get_primary_cpus() - returns a CPU mask for the first
>> bringup iteration.
>
> Why are there two?
This pair is after the existing cpuhp_smt_aware() and
cpuhp_get_primary_thread_mask() pair in kernel/cpu.c
I think cpu_primary_thread_mask alone isn't that obvious to indicate SMT
on or off. So similarly arch_cpuhp_primary_aware() provides an explicit
indication for the if statement.
>
> Why are there even accessors at all when you can simply use
> cpu_primary_thread_mask whereever you need it and drop all that gunk here and
> in the next patch?
>
The series directs the bringup code to select different masks depending
on the uniform scope reported by CPUID. That's very x86-ish code thus in
arch/x86. So I ended up with accessors connecting to that x86 part.
But in a bigger picture, this is a part of the early loading support
along with patch2/3/7. Introducing cpu_primary_core_mask itself in
patch3 may be seen an overkill, TBH. In fact, the latency impact on
early loading (when without uniform support) wasn't observed that much
in practice. But, OTOH, one may also argue the loading scope should be
consistent on both ends. So I think it is worth settling down on which
approach to go.
Thanks,
Chang
next prev parent reply other threads:[~2026-09-30 4:45 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-12 0:08 [PATCH RFC v1 0/8] x86/microcode: Enable uniform feature Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 1/8] cpu/hotplug: Allow architecture-specific primary CPU bringup Chang S. Bae
2026-09-30 0:20 ` Borislav Petkov
2026-09-30 4:44 ` Chang S. Bae [this message]
2026-09-30 4:57 ` Borislav Petkov
2026-09-12 0:08 ` [PATCH RFC v1 2/8] x86/hotplug: Implement SMT-primary selection for parallel bringup Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 3/8] x86/cpu/topology: Introduce primary core mask Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 4/8] x86/microcode: Extend struct microcode_ops for uniform loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 5/8] x86/microcode: Clarify online enforcement with " Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 6/8] x86/microcode: Support uniform scope for late loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 7/8] x86/microcode/intel: Support uniform scope for early loading Chang S. Bae
2026-09-12 0:08 ` [PATCH RFC v1 8/8] x86/microcode/intel: Enable uniform loading Chang S. Bae
2026-09-16 0:45 ` [PATCH RFC v1 0/8] x86/microcode: Enable uniform feature Borislav Petkov
2026-09-16 23:10 ` Chang S. Bae
2026-09-29 18:47 ` Borislav Petkov
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