From: James Clark <jjc@jclark.com>
To: Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Richard Cochran <richardcochran@gmail.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Lee Jones <lee@kernel.org>
Cc: Siddharth Vadapalli <s-vadapalli@ti.com>,
Roger Quadros <rogerq@kernel.org>,
Sebastian Andrzej Siewior <bigeasy@linutronix.de>,
Martin Kaistra <martin.kaistra@linutronix.de>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Rahul Sharma <r-sharma3@ti.com>,
Robert Nelson <robertcnelson@gmail.com>,
Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
Chintan Vankar <c-vankar@ti.com>,
netdev@vger.kernel.org, devicetree@vger.kernel.org,
mfd@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH net-next 2/3] dt-bindings: net: ti,k3-am654-cpts: add ti,gtc-push
Date: Tue, 10 Nov 2026 11:24:02 +0700 [thread overview]
Message-ID: <680b4e98af630c4759dbdf73b53926ec5f87fc3b.1794284248.git.jjc@jclark.com> (raw)
In-Reply-To: <cover.1794284248.git.jjc@jclark.com>
The Global Timebase Counter (GTC) of TI K3 SoCs is the system counter,
the one the Arm cores read as the architected counter. It can export one
of its counter bits, selected by GTC_CFG0_PUSHEVT, as a push event
output, and the Time Sync Router can route that output to one of the
CPTS hardware timestamp push inputs (HWx_TS_PUSH). The CPTS then
timestamps edges that fall at known counter values, which gives pairs of
CPTS and system counter values.
Add an optional ti,gtc-push property giving the GTC CFG0 syscon and the
HWx_TS_PUSH input the push event is routed to. The CPTS driver uses this
to write GTC_CFG0_PUSHEVT. The router itself is configured separately, as
it is for ti,pps.
Signed-off-by: James Clark <jjc@jclark.com>
---
.../bindings/net/ti,k3-am654-cpts.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
index 3572749147fb..7bf5bedc2b9c 100644
--- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpts.yaml
@@ -101,6 +101,23 @@ properties:
The pair of HWx_TS_PUSH input and TS_GENFy output indexes used for
PPS events generation. Platform/board specific.
+ ti,gtc-push:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to the Global Timebase Counter (GTC) CFG0
+ syscon
+ - description: HWx_TS_PUSH input index (0-based) the GTC push event
+ is routed to
+ maximum: 7
+ description: |
+ The GTC is the SoC's system counter (the Arm architected counter). Its
+ push event output, one counter bit selected by GTC_CFG0_PUSHEVT, reaches
+ a CPTS hardware timestamp push input through the Time Sync Router. With
+ this property the CPTS timestamps that signal to provide hardware
+ cross-timestamps of the CPTS and the system counter. The router is
+ configured separately. Platform/board specific.
+
refclk-mux:
type: object
additionalProperties: false
--
2.56.0
next prev parent reply other threads:[~2026-11-10 4:24 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 4:24 [PATCH net-next 0/3] net: ethernet: ti: am65-cpts: add PTP_SYS_OFFSET_PRECISE support James Clark
2026-11-10 4:24 ` [PATCH net-next 1/3] dt-bindings: mfd: syscon: add ti,am654-gtc James Clark
2026-11-10 4:24 ` James Clark [this message]
2026-11-10 4:24 ` [PATCH net-next 3/3] net: ethernet: ti: am65-cpts: implement PTP_SYS_OFFSET_PRECISE James Clark
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