[PATCH V3 0/3] Add support for uartps controller reset

[PATCH V3 0/3] Add support for uartps controller reset

[Manikanta Guntupalli]

Add optional resets property for UART nodes.
Add support for uartps controller reset.
---
Changes for V2:
Added ack signature for binding patch.
Remove check for reset_control_deassert, as reset_control_deassert
function internally has NULL check.

Changes for V3:
Corrected typo in subject of binding patch.

Manikanta Guntupalli (3):
  dt-bindings: serial: cdns,uart: Add optional reset property
  arm64: zynqmp: Add resets property for UART nodes
  tty: serial: uartps: Add support for uartps controller reset

 .../devicetree/bindings/serial/cdns,uart.yaml     |  3 +++
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi            |  2 ++
 drivers/tty/serial/xilinx_uartps.c                | 15 +++++++++++++++
 3 files changed, 20 insertions(+)

-- 
2.25.1

[PATCH V3 1/3] dt-bindings: serial: cdns,uart: Add optional reset property

[Manikanta Guntupalli]

Add optional reset device-tree property to the uartps controller.

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Changes for V2:
Added ack signature.
Changes for V3:
Corrected typo in subject.
---
 Documentation/devicetree/bindings/serial/cdns,uart.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/serial/cdns,uart.yaml b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
index 2129247d7c81..d7f047b0bf24 100644
--- a/Documentation/devicetree/bindings/serial/cdns,uart.yaml
+++ b/Documentation/devicetree/bindings/serial/cdns,uart.yaml
@@ -46,6 +46,9 @@ properties:
   power-domains:
     maxItems: 1
 
+  resets:
+    maxItems: 1
+
 required:
   - compatible
   - reg
-- 
2.25.1

[PATCH V3 2/3] arm64: zynqmp: Add resets property for UART nodes

[Manikanta Guntupalli]

Add resets property for UART0 and UART1 nodes

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
---
Changes for V2:
None.
Changes for V3:
None.
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 25d20d803230..935504424ec6 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -906,6 +906,7 @@ uart0: serial@ff000000 {
 			reg = <0x0 0xff000000 0x0 0x1000>;
 			clock-names = "uart_clk", "pclk";
 			power-domains = <&zynqmp_firmware PD_UART_0>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_UART0>;
 		};
 
 		uart1: serial@ff010000 {
@@ -917,6 +918,7 @@ uart1: serial@ff010000 {
 			reg = <0x0 0xff010000 0x0 0x1000>;
 			clock-names = "uart_clk", "pclk";
 			power-domains = <&zynqmp_firmware PD_UART_1>;
+			resets = <&zynqmp_reset ZYNQMP_RESET_UART1>;
 		};
 
 		usb0: usb@ff9d0000 {
-- 
2.25.1

[PATCH V3 3/3] tty: serial: uartps: Add support for uartps controller reset

[Manikanta Guntupalli]

Add support for an optional reset for the uartps controller using
the reset driver. If the uartps node contains the "resets" property,
then cdns_uart_startup performs uartps controller non-pulse out of reset
and reset in exit path.

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
---
Changes for V2:
Remove check for reset_control_deassert, as reset_control_deassert
function internally has NULL check.
Changes for V3:
None.
---
 drivers/tty/serial/xilinx_uartps.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index de3487206bcb..2acfcea403ce 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio/consumer.h>
 #include <linux/delay.h>
+#include <linux/reset.h>
 
 #define CDNS_UART_TTY_NAME	"ttyPS"
 #define CDNS_UART_NAME		"xuartps"
@@ -198,6 +199,7 @@ MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
  * @gpiod_rts:		Pointer to the gpio descriptor
  * @rs485_tx_started:	RS485 tx state
  * @tx_timer:		Timer for tx
+ * @rstc:		Pointer to the reset control
  */
 struct cdns_uart {
 	struct uart_port	*port;
@@ -211,6 +213,7 @@ struct cdns_uart {
 	struct gpio_desc	*gpiod_rts;
 	bool			rs485_tx_started;
 	struct hrtimer		tx_timer;
+	struct reset_control	*rstc;
 };
 struct cdns_platform_data {
 	u32 quirks;
@@ -948,6 +951,10 @@ static int cdns_uart_startup(struct uart_port *port)
 
 	is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
 
+	ret = reset_control_deassert(cdns_uart->rstc);
+	if (ret)
+		return ret;
+
 	uart_port_lock_irqsave(port, &flags);
 
 	/* Disable the TX and RX */
@@ -1721,6 +1728,13 @@ static int cdns_uart_probe(struct platform_device *pdev)
 		dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
 	}
 
+	cdns_uart_data->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+	if (IS_ERR(cdns_uart_data->rstc)) {
+		rc = PTR_ERR(cdns_uart_data->rstc);
+		dev_err_probe(&pdev->dev, rc, "Cannot get UART reset\n");
+		goto err_out_unregister_driver;
+	}
+
 	rc = clk_prepare_enable(cdns_uart_data->pclk);
 	if (rc) {
 		dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
@@ -1881,6 +1895,7 @@ static void cdns_uart_remove(struct platform_device *pdev)
 	if (console_port == port)
 		console_port = NULL;
 #endif
+	reset_control_assert(cdns_uart_data->rstc);
 
 	if (!--instances)
 		uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
-- 
2.25.1

Re: [PATCH V3 2/3] arm64: zynqmp: Add resets property for UART nodes

[Michal Simek]

On 4/25/24 08:23, Manikanta Guntupalli wrote:
> Add resets property for UART0 and UART1 nodes
> 
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
> ---
> Changes for V2:
> None.
> Changes for V3:
> None.
> ---
>   arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 2 ++
>   1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 25d20d803230..935504424ec6 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -906,6 +906,7 @@ uart0: serial@ff000000 {
>   			reg = <0x0 0xff000000 0x0 0x1000>;
>   			clock-names = "uart_clk", "pclk";
>   			power-domains = <&zynqmp_firmware PD_UART_0>;
> +			resets = <&zynqmp_reset ZYNQMP_RESET_UART0>;
>   		};
>   
>   		uart1: serial@ff010000 {
> @@ -917,6 +918,7 @@ uart1: serial@ff010000 {
>   			reg = <0x0 0xff010000 0x0 0x1000>;
>   			clock-names = "uart_clk", "pclk";
>   			power-domains = <&zynqmp_firmware PD_UART_1>;
> +			resets = <&zynqmp_reset ZYNQMP_RESET_UART1>;
>   		};
>   
>   		usb0: usb@ff9d0000 {

This patch should likely go via my tree but if Greg wants to take it directly 
that's fine for me.
In that case here is my
Acked-by: Michal Simek <michal.simek@amd.com>

Thanks,
Michal