* [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192
2023-05-29 16:46 [PATCH v3 0/5] Add LVTS support for mt8192 Bernhard Rosenkränzer
@ 2023-05-29 16:46 ` Bernhard Rosenkränzer
2023-05-30 7:02 ` Matthias Brugger
2023-05-29 16:46 ` [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Bernhard Rosenkränzer
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 16:46 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS thermal controller definition for MT8192.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
.../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
index 8fa5a46675c46..5e9eb62174268 100644
--- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
@@ -26,4 +26,23 @@
#define MT8195_AP_CAM0 15
#define MT8195_AP_CAM1 16
+#define MT8192_MCU_BIG_CPU0 0
+#define MT8192_MCU_BIG_CPU1 1
+#define MT8192_MCU_BIG_CPU2 2
+#define MT8192_MCU_BIG_CPU3 3
+#define MT8192_MCU_LITTLE_CPU0 4
+#define MT8192_MCU_LITTLE_CPU1 5
+#define MT8192_MCU_LITTLE_CPU2 6
+#define MT8192_MCU_LITTLE_CPU3 7
+
+#define MT8192_AP_VPU0 8
+#define MT8192_AP_VPU1 9
+#define MT8192_AP_GPU0 10
+#define MT8192_AP_GPU1 11
+#define MT8192_AP_INFRA 12
+#define MT8192_AP_CAM 13
+#define MT8192_AP_MD0 14
+#define MT8192_AP_MD1 15
+#define MT8192_AP_MD2 16
+
#endif /* __MEDIATEK_LVTS_DT_H */
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for mt8192
2023-05-29 16:46 ` [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition " Bernhard Rosenkränzer
@ 2023-05-30 7:02 ` Matthias Brugger
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Brugger @ 2023-05-30 7:02 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano,
angelogioacchino.delregno, rafael, amitk, rui.zhang, robh+dt,
krzysztof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
On 29/05/2023 18:46, Bernhard Rosenkränzer wrote:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add LVTS thermal controller definition for MT8192.
>
> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> .../thermal/mediatek,lvts-thermal.h | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/include/dt-bindings/thermal/mediatek,lvts-thermal.h b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
> index 8fa5a46675c46..5e9eb62174268 100644
> --- a/include/dt-bindings/thermal/mediatek,lvts-thermal.h
> +++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
> @@ -26,4 +26,23 @@
> #define MT8195_AP_CAM0 15
> #define MT8195_AP_CAM1 16
>
> +#define MT8192_MCU_BIG_CPU0 0
> +#define MT8192_MCU_BIG_CPU1 1
> +#define MT8192_MCU_BIG_CPU2 2
> +#define MT8192_MCU_BIG_CPU3 3
> +#define MT8192_MCU_LITTLE_CPU0 4
> +#define MT8192_MCU_LITTLE_CPU1 5
> +#define MT8192_MCU_LITTLE_CPU2 6
> +#define MT8192_MCU_LITTLE_CPU3 7
> +
> +#define MT8192_AP_VPU0 8
> +#define MT8192_AP_VPU1 9
> +#define MT8192_AP_GPU0 10
> +#define MT8192_AP_GPU1 11
> +#define MT8192_AP_INFRA 12
> +#define MT8192_AP_CAM 13
> +#define MT8192_AP_MD0 14
> +#define MT8192_AP_MD1 15
> +#define MT8192_AP_MD2 16
> +
> #endif /* __MEDIATEK_LVTS_DT_H */
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
2023-05-29 16:46 [PATCH v3 0/5] Add LVTS support for mt8192 Bernhard Rosenkränzer
2023-05-29 16:46 ` [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition " Bernhard Rosenkränzer
@ 2023-05-29 16:46 ` Bernhard Rosenkränzer
2023-05-30 7:09 ` Matthias Brugger
2023-05-29 16:46 ` [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Bernhard Rosenkränzer
` (2 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 16:46 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add suspend and resume support to LVTS driver.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d0a3f95b7884b..5ea8a9d569ea6 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev)
return 0;
}
+static int lvts_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct lvts_domain *lvts_td;
+ int i;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
+
+ clk_disable_unprepare(lvts_td->clk);
+
+ return 0;
+}
+
+static int lvts_resume(struct platform_device *pdev)
+{
+ struct lvts_domain *lvts_td;
+ int i, ret;
+
+ lvts_td = platform_get_drvdata(pdev);
+
+ ret = clk_prepare_enable(lvts_td->clk);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
+ lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
+
+ return 0;
+}
+
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
{
.cal_offset = { 0x04, 0x07 },
@@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
static struct platform_driver lvts_driver = {
.probe = lvts_probe,
.remove = lvts_remove,
+ .suspend = lvts_suspend,
+ .resume = lvts_resume,
.driver = {
.name = "mtk-lvts-thermal",
.of_match_table = lvts_of_match,
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume
2023-05-29 16:46 ` [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Bernhard Rosenkränzer
@ 2023-05-30 7:09 ` Matthias Brugger
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Brugger @ 2023-05-30 7:09 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano,
angelogioacchino.delregno, rafael, amitk, rui.zhang, robh+dt,
krzysztof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
On 29/05/2023 18:46, Bernhard Rosenkränzer wrote:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add suspend and resume support to LVTS driver.
>
> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/thermal/mediatek/lvts_thermal.c | 34 +++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
>
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index d0a3f95b7884b..5ea8a9d569ea6 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -1169,6 +1169,38 @@ static int lvts_remove(struct platform_device *pdev)
> return 0;
> }
>
> +static int lvts_suspend(struct platform_device *pdev, pm_message_t state)
> +{
> + struct lvts_domain *lvts_td;
> + int i;
> +
> + lvts_td = platform_get_drvdata(pdev);
> +
> + for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
> + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
> +
> + clk_disable_unprepare(lvts_td->clk);
> +
> + return 0;
> +}
> +
> +static int lvts_resume(struct platform_device *pdev)
> +{
> + struct lvts_domain *lvts_td;
> + int i, ret;
> +
> + lvts_td = platform_get_drvdata(pdev);
> +
> + ret = clk_prepare_enable(lvts_td->clk);
> + if (ret)
> + return ret;
> +
> + for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
> + lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true);
> +
> + return 0;
> +}
> +
> static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
> {
> .cal_offset = { 0x04, 0x07 },
> @@ -1268,6 +1300,8 @@ MODULE_DEVICE_TABLE(of, lvts_of_match);
> static struct platform_driver lvts_driver = {
> .probe = lvts_probe,
> .remove = lvts_remove,
> + .suspend = lvts_suspend,
> + .resume = lvts_resume,
> .driver = {
> .name = "mtk-lvts-thermal",
> .of_match_table = lvts_of_match,
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
2023-05-29 16:46 [PATCH v3 0/5] Add LVTS support for mt8192 Bernhard Rosenkränzer
2023-05-29 16:46 ` [PATCH v3 1/5] dt-bindings: thermal: mediatek: Add LVTS thermal controller definition " Bernhard Rosenkränzer
2023-05-29 16:46 ` [PATCH v3 2/5] thermal/drivers/mediatek/lvts_thermal: Add suspend and resume Bernhard Rosenkränzer
@ 2023-05-29 16:46 ` Bernhard Rosenkränzer
2023-05-30 7:12 ` Matthias Brugger
2023-05-29 16:46 ` [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Bernhard Rosenkränzer
2023-05-29 16:46 ` [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Bernhard Rosenkränzer
4 siblings, 1 reply; 12+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 16:46 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add LVTS Driver support for MT8192.
Co-developed-by : Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index 5ea8a9d569ea6..d5e5214784ece 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -80,6 +80,7 @@
#define LVTS_MSR_FILTERED_MODE 1
#define LVTS_HW_SHUTDOWN_MT8195 105000
+#define LVTS_HW_SHUTDOWN_MT8192 105000
static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
static int coeff_b = LVTS_COEFF_B;
@@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
}
};
+static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
+ {
+ .cal_offset = { 0x04, 0x08 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU0 },
+ { .dt_id = MT8192_MCU_BIG_CPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x0c, 0x10 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_BIG_CPU2 },
+ { .dt_id = MT8192_MCU_BIG_CPU3 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ },
+ {
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_MCU_LITTLE_CPU0 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU1 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU2 },
+ { .dt_id = MT8192_MCU_LITTLE_CPU3 }
+ },
+ .num_lvts_sensor = 4,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ .mode = LVTS_MSR_FILTERED_MODE,
+ }
+};
+
+static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
+ {
+ .cal_offset = { 0x24, 0x28 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_VPU0 },
+ { .dt_id = MT8192_AP_VPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x0,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x2c, 0x30 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_GPU0 },
+ { .dt_id = MT8192_AP_GPU1 }
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x100,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x34, 0x38 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_INFRA },
+ { .dt_id = MT8192_AP_CAM },
+ },
+ .num_lvts_sensor = 2,
+ .offset = 0x200,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ },
+ {
+ .cal_offset = { 0x3c, 0x40, 0x44 },
+ .lvts_sensor = {
+ { .dt_id = MT8192_AP_MD0 },
+ { .dt_id = MT8192_AP_MD1 },
+ { .dt_id = MT8192_AP_MD2 }
+ },
+ .num_lvts_sensor = 3,
+ .offset = 0x300,
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
+ }
+};
+
static const struct lvts_data mt8195_lvts_mcu_data = {
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
@@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = {
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
};
+static const struct lvts_data mt8192_lvts_mcu_data = {
+ .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
+};
+
+static const struct lvts_data mt8192_lvts_ap_data = {
+ .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
+ .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
+};
+
static const struct of_device_id lvts_of_match[] = {
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
+ { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
+ { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
{},
};
MODULE_DEVICE_TABLE(of, lvts_of_match);
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support
2023-05-29 16:46 ` [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Bernhard Rosenkränzer
@ 2023-05-30 7:12 ` Matthias Brugger
0 siblings, 0 replies; 12+ messages in thread
From: Matthias Brugger @ 2023-05-30 7:12 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano,
angelogioacchino.delregno, rafael, amitk, rui.zhang, robh+dt,
krzysztof.kozlowski+dt, rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
On 29/05/2023 18:46, Bernhard Rosenkränzer wrote:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add LVTS Driver support for MT8192.
>
> Co-developed-by : Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Signed-off-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> ---
> drivers/thermal/mediatek/lvts_thermal.c | 95 +++++++++++++++++++++++++
> 1 file changed, 95 insertions(+)
>
> diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
> index 5ea8a9d569ea6..d5e5214784ece 100644
> --- a/drivers/thermal/mediatek/lvts_thermal.c
> +++ b/drivers/thermal/mediatek/lvts_thermal.c
> @@ -80,6 +80,7 @@
> #define LVTS_MSR_FILTERED_MODE 1
>
> #define LVTS_HW_SHUTDOWN_MT8195 105000
> +#define LVTS_HW_SHUTDOWN_MT8192 105000
>
> static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
> static int coeff_b = LVTS_COEFF_B;
> @@ -1280,6 +1281,88 @@ static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
> }
> };
>
> +static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = {
> + {
> + .cal_offset = { 0x04, 0x08 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_MCU_BIG_CPU0 },
> + { .dt_id = MT8192_MCU_BIG_CPU1 }
> + },
> + .num_lvts_sensor = 2,
> + .offset = 0x0,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + .mode = LVTS_MSR_FILTERED_MODE,
> + },
> + {
> + .cal_offset = { 0x0c, 0x10 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_MCU_BIG_CPU2 },
> + { .dt_id = MT8192_MCU_BIG_CPU3 }
> + },
> + .num_lvts_sensor = 2,
> + .offset = 0x100,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + .mode = LVTS_MSR_FILTERED_MODE,
> + },
> + {
> + .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_MCU_LITTLE_CPU0 },
> + { .dt_id = MT8192_MCU_LITTLE_CPU1 },
> + { .dt_id = MT8192_MCU_LITTLE_CPU2 },
> + { .dt_id = MT8192_MCU_LITTLE_CPU3 }
> + },
> + .num_lvts_sensor = 4,
> + .offset = 0x200,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + .mode = LVTS_MSR_FILTERED_MODE,
> + }
> +};
> +
> +static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = {
> + {
> + .cal_offset = { 0x24, 0x28 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_AP_VPU0 },
> + { .dt_id = MT8192_AP_VPU1 }
> + },
> + .num_lvts_sensor = 2,
> + .offset = 0x0,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + },
> + {
> + .cal_offset = { 0x2c, 0x30 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_AP_GPU0 },
> + { .dt_id = MT8192_AP_GPU1 }
> + },
> + .num_lvts_sensor = 2,
> + .offset = 0x100,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + },
> + {
> + .cal_offset = { 0x34, 0x38 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_AP_INFRA },
> + { .dt_id = MT8192_AP_CAM },
> + },
> + .num_lvts_sensor = 2,
> + .offset = 0x200,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + },
> + {
> + .cal_offset = { 0x3c, 0x40, 0x44 },
> + .lvts_sensor = {
> + { .dt_id = MT8192_AP_MD0 },
> + { .dt_id = MT8192_AP_MD1 },
> + { .dt_id = MT8192_AP_MD2 }
> + },
> + .num_lvts_sensor = 3,
> + .offset = 0x300,
> + .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8192,
> + }
> +};
> +
> static const struct lvts_data mt8195_lvts_mcu_data = {
> .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
> .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
> @@ -1290,9 +1373,21 @@ static const struct lvts_data mt8195_lvts_ap_data = {
> .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
> };
>
> +static const struct lvts_data mt8192_lvts_mcu_data = {
> + .lvts_ctrl = mt8192_lvts_mcu_data_ctrl,
> + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl),
> +};
> +
> +static const struct lvts_data mt8192_lvts_ap_data = {
> + .lvts_ctrl = mt8192_lvts_ap_data_ctrl,
> + .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl),
> +};
> +
> static const struct of_device_id lvts_of_match[] = {
> { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
> { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
> + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data },
> + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data },
> {},
> };
> MODULE_DEVICE_TABLE(of, lvts_of_match);
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
2023-05-29 16:46 [PATCH v3 0/5] Add LVTS support for mt8192 Bernhard Rosenkränzer
` (2 preceding siblings ...)
2023-05-29 16:46 ` [PATCH v3 3/5] thermal/drivers/mediatek/lvts_thermal: Add mt8192 support Bernhard Rosenkränzer
@ 2023-05-29 16:46 ` Bernhard Rosenkränzer
2023-05-30 6:59 ` AngeloGioacchino Del Regno
2023-05-29 16:46 ` [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Bernhard Rosenkränzer
4 siblings, 1 reply; 12+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 16:46 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Add thermal nodes and thermal zones for the mt8192.
The mt8192 SoC has several hotspots around the CPUs.
Specify the targeted temperature threshold to apply the mitigation
and define the associated cooling devices.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: cosmetic changes]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
1 file changed, 454 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 5c30caf740265..330c5bb4ebc85 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
#include <dt-bindings/reset/mt8192-resets.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
/ {
compatible = "mediatek,mt8192";
@@ -71,6 +73,7 @@ cpu0: cpu@0 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu1: cpu@100 {
@@ -88,6 +91,7 @@ cpu1: cpu@100 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu2: cpu@200 {
@@ -105,6 +109,7 @@ cpu2: cpu@200 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu3: cpu@300 {
@@ -122,6 +127,7 @@ cpu3: cpu@300 {
d-cache-sets = <128>;
next-level-cache = <&l2_0>;
capacity-dmips-mhz = <530>;
+ #cooling-cells = <2>;
};
cpu4: cpu@400 {
@@ -139,6 +145,7 @@ cpu4: cpu@400 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu5: cpu@500 {
@@ -156,6 +163,7 @@ cpu5: cpu@500 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu6: cpu@600 {
@@ -173,6 +181,7 @@ cpu6: cpu@600 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu7: cpu@700 {
@@ -190,6 +199,7 @@ cpu7: cpu@700 {
d-cache-sets = <256>;
next-level-cache = <&l2_1>;
capacity-dmips-mhz = <1024>;
+ #cooling-cells = <2>;
};
cpu-map {
@@ -771,6 +781,17 @@ spi0: spi@1100a000 {
status = "disabled";
};
+ lvts_ap: thermal-sensor@1100b000 {
+ compatible = "mediatek,mt8192-lvts-ap";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
pwm0: pwm@1100e000 {
compatible = "mediatek,mt8183-disp-pwm";
reg = <0 0x1100e000 0 0x1000>;
@@ -1097,6 +1118,17 @@ nor_flash: spi@11234000 {
status = "disabled";
};
+ lvts_mcu: thermal-sensor@11278000 {
+ compatible = "mediatek,mt8192-lvts-mcu";
+ reg = <0 0x11278000 0 0x1000>;
+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_THERM>;
+ resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
+ nvmem-cells = <&lvts_e_data1>;
+ nvmem-cell-names = "lvts-calib-data-1";
+ #thermal-sensor-cells = <1>;
+ };
+
efuse: efuse@11c10000 {
compatible = "mediatek,mt8192-efuse", "mediatek,efuse";
reg = <0 0x11c10000 0 0x1000>;
@@ -1823,4 +1855,426 @@ larb2: larb@1f002000 {
power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
};
};
+
+ thermal_zones: thermal-zones {
+ cpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU0>;
+
+ trips {
+ cpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu0_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU1>;
+
+ trips {
+ cpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu1_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU2>;
+
+ trips {
+ cpu2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu2_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu3-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_LITTLE_CPU3>;
+
+ trips {
+ cpu3_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu3_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu3_alert>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu4-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU0>;
+
+ trips {
+ cpu4_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu4_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu4_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu5-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU1>;
+
+ trips {
+ cpu5_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu5_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu5_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu6-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU2>;
+
+ trips {
+ cpu6_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu6_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu6_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ cpu7-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_mcu MT8192_MCU_BIG_CPU3>;
+
+ trips {
+ cpu7_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu7_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu7_alert>;
+ cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ vpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU0>;
+
+ trips {
+ vpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ vpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_VPU1>;
+
+ trips {
+ vpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ vpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU0>;
+
+ trips {
+ gpu0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpu1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_GPU1>;
+
+ trips {
+ gpu1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ gpu1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ infra-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_INFRA>;
+
+ trips {
+ infra_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ infra_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ cam-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_CAM>;
+
+ trips {
+ cam_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cam_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md0-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD0>;
+
+ trips {
+ md0_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md0_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md1-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD1>;
+
+ trips {
+ md1_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md1_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ md2-thermal {
+ polling-delay = <1000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&lvts_ap MT8192_AP_MD2>;
+
+ trips {
+ md2_alert: trip-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ md2_crit: trip-crit {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
};
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones
2023-05-29 16:46 ` [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Bernhard Rosenkränzer
@ 2023-05-30 6:59 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 12+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-05-30 6:59 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
Il 29/05/23 18:46, Bernhard Rosenkränzer ha scritto:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Add thermal nodes and thermal zones for the mt8192.
> The mt8192 SoC has several hotspots around the CPUs.
> Specify the targeted temperature threshold to apply the mitigation
> and define the associated cooling devices.
>
> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> [bero@baylibre.com: cosmetic changes]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 454 +++++++++++++++++++++++
> 1 file changed, 454 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 5c30caf740265..330c5bb4ebc85 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -14,6 +14,8 @@
> #include <dt-bindings/phy/phy.h>
> #include <dt-bindings/power/mt8192-power.h>
> #include <dt-bindings/reset/mt8192-resets.h>
> +#include <dt-bindings/thermal/thermal.h>
> +#include <dt-bindings/thermal/mediatek,lvts-thermal.h>
>
> / {
> compatible = "mediatek,mt8192";
> @@ -71,6 +73,7 @@ cpu0: cpu@0 {
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> capacity-dmips-mhz = <530>;
> + #cooling-cells = <2>;
> };
>
> cpu1: cpu@100 {
> @@ -88,6 +91,7 @@ cpu1: cpu@100 {
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> capacity-dmips-mhz = <530>;
> + #cooling-cells = <2>;
> };
>
> cpu2: cpu@200 {
> @@ -105,6 +109,7 @@ cpu2: cpu@200 {
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> capacity-dmips-mhz = <530>;
> + #cooling-cells = <2>;
> };
>
> cpu3: cpu@300 {
> @@ -122,6 +127,7 @@ cpu3: cpu@300 {
> d-cache-sets = <128>;
> next-level-cache = <&l2_0>;
> capacity-dmips-mhz = <530>;
> + #cooling-cells = <2>;
> };
>
> cpu4: cpu@400 {
> @@ -139,6 +145,7 @@ cpu4: cpu@400 {
> d-cache-sets = <256>;
> next-level-cache = <&l2_1>;
> capacity-dmips-mhz = <1024>;
> + #cooling-cells = <2>;
> };
>
> cpu5: cpu@500 {
> @@ -156,6 +163,7 @@ cpu5: cpu@500 {
> d-cache-sets = <256>;
> next-level-cache = <&l2_1>;
> capacity-dmips-mhz = <1024>;
> + #cooling-cells = <2>;
> };
>
> cpu6: cpu@600 {
> @@ -173,6 +181,7 @@ cpu6: cpu@600 {
> d-cache-sets = <256>;
> next-level-cache = <&l2_1>;
> capacity-dmips-mhz = <1024>;
> + #cooling-cells = <2>;
> };
>
> cpu7: cpu@700 {
> @@ -190,6 +199,7 @@ cpu7: cpu@700 {
> d-cache-sets = <256>;
> next-level-cache = <&l2_1>;
> capacity-dmips-mhz = <1024>;
> + #cooling-cells = <2>;
> };
>
> cpu-map {
> @@ -771,6 +781,17 @@ spi0: spi@1100a000 {
> status = "disabled";
> };
>
> + lvts_ap: thermal-sensor@1100b000 {
> + compatible = "mediatek,mt8192-lvts-ap";
> + reg = <0 0x1100b000 0 0x1000>;
reg = <0 0x1100b000 0 0xc00>;
...as 0xc00 should be more than sufficient. This is important for later
when we'll get SVS support up (which is in the LVTS-AP iospace range).
Regards,
Angelo
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation
2023-05-29 16:46 [PATCH v3 0/5] Add LVTS support for mt8192 Bernhard Rosenkränzer
` (3 preceding siblings ...)
2023-05-29 16:46 ` [PATCH v3 4/5] arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones Bernhard Rosenkränzer
@ 2023-05-29 16:46 ` Bernhard Rosenkränzer
2023-05-30 7:00 ` AngeloGioacchino Del Regno
4 siblings, 1 reply; 12+ messages in thread
From: Bernhard Rosenkränzer @ 2023-05-29 16:46 UTC (permalink / raw)
To: daniel.lezcano, angelogioacchino.delregno, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
From: Balsam CHIHI <bchihi@baylibre.com>
Update LVTS calibration data documentation for mt8192 and mt8195.
Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
[bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
---
drivers/thermal/mediatek/lvts_thermal.c | 31 +++++++++++++++++++++++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c
index d5e5214784ece..9185d02003633 100644
--- a/drivers/thermal/mediatek/lvts_thermal.c
+++ b/drivers/thermal/mediatek/lvts_thermal.c
@@ -531,7 +531,8 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* The efuse blob values follows the sensor enumeration per thermal
* controller. The decoding of the stream is as follow:
*
- * stream index map for MCU Domain :
+ * MT8195 :
+ * Stream index map for MCU Domain mt8195 :
*
* <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
@@ -542,7 +543,7 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
* 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
*
- * stream index map for AP Domain :
+ * Stream index map for AP Domain mt8195 :
*
* <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
* 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
@@ -556,6 +557,32 @@ static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
* <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
* 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
*
+ * MT8192 :
+ * Stream index map for MCU Domain mt8192 :
+ *
+ * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
+ * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13
+ *
+ * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
+ * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23
+ *
+ * Stream index map for AP Domain mt8192 :
+ *
+ * <-----sensor#0-----> <-----sensor#1----->
+ * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B
+ *
+ * <-----sensor#2-----> <-----sensor#3----->
+ * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
+ *
+ * <-----sensor#4-----> <-----sensor#5----->
+ * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B
+ *
+ * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8----->
+ * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47
+ *
* The data description gives the offset of the calibration data in
* this bytes stream for each sensor.
*/
--
2.41.0.rc2
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation
2023-05-29 16:46 ` [PATCH v3 5/5] thermal/drivers/mediatek/lvts_thermal: Update calibration data documentation Bernhard Rosenkränzer
@ 2023-05-30 7:00 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 12+ messages in thread
From: AngeloGioacchino Del Regno @ 2023-05-30 7:00 UTC (permalink / raw)
To: Bernhard Rosenkränzer, daniel.lezcano, rafael, amitk,
rui.zhang, matthias.bgg, robh+dt, krzysztof.kozlowski+dt,
rdunlap, ye.xingchen, p.zabel
Cc: linux-pm, linux-kernel, linux-arm-kernel, linux-mediatek,
devicetree, wenst, james.lo, rex-bc.chen, nfraprado, abailon,
amergnat, khilman
Il 29/05/23 18:46, Bernhard Rosenkränzer ha scritto:
> From: Balsam CHIHI <bchihi@baylibre.com>
>
> Update LVTS calibration data documentation for mt8192 and mt8195.
>
> Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> [bero@baylibre.com: Fix issues pointed out by Nícolas F. R. A. Prado <nfraprado@collabora.com>]
> Signed-off-by: Bernhard Rosenkränzer <bero@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
^ permalink raw reply [flat|nested] 12+ messages in thread