From: Paul Walmsley <pjw@kernel.org>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-kernel@vger.kernel.org, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Andy Chiu <andybnac@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>,
"open list:RISC-V ARCHITECTURE"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask
Date: Sun, 4 Oct 2026 16:21:29 -0600 (MDT) [thread overview]
Message-ID: <6ce0769c-4683-0e62-e3b2-56b3300a45a2@kernel.org> (raw)
In-Reply-To: <20260911194233.3379532-1-aurelien@aurel32.net>
On Fri, 11 Sep 2026, Aurelien Jarno wrote:
> RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
> Replace GENMASK(12, 0) by GENMASK(11, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Thanks, queued for v7.4.
- Paul
prev parent reply other threads:[~2026-10-04 22:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 19:42 Aurelien Jarno
2026-10-04 3:44 ` Jisheng Zhang
2026-10-04 22:21 ` Paul Walmsley [this message]
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