From: Jisheng Zhang <jszhang@kernel.org>
To: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-kernel@vger.kernel.org, Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>, Andy Chiu <andybnac@gmail.com>,
Conor Dooley <conor.dooley@microchip.com>,
"open list:RISC-V ARCHITECTURE" <linux-riscv@lists.infradead.org>
Subject: Re: [PATCH] riscv: fix RVG_SYSTEM_CSR_MASK width mask
Date: Sun, 4 Oct 2026 11:44:38 +0800 [thread overview]
Message-ID: <asHLphURjbEyu6j_@xhacker> (raw)
In-Reply-To: <20260911194233.3379532-1-aurelien@aurel32.net>
On Fri, Sep 11, 2026 at 09:42:33PM +0200, Aurelien Jarno wrote:
> RVG_SYSTEM_CSR_MASK should be 12 bits [31:20], shifted down by 20 bits.
> Replace GENMASK(12, 0) by GENMASK(11, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> arch/riscv/include/asm/insn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index c3005573e8c9..ad348d8b8857 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -142,7 +142,7 @@
> #define RVG_OPCODE_JAL 0x6f
> #define RVG_OPCODE_SYSTEM 0x73
> #define RVG_SYSTEM_CSR_OFF 20
> -#define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
> +#define RVG_SYSTEM_CSR_MASK GENMASK(11, 0)
>
> /* parts of opcode for RVF, RVD and RVQ */
> #define RVFDQ_FL_FS_WIDTH_OFF 12
> --
> 2.53.0
>
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2026-10-04 4:04 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-11 19:42 Aurelien Jarno
2026-10-04 3:44 ` Jisheng Zhang [this message]
2026-10-04 22:21 ` Paul Walmsley
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