From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
To: Stephen Boyd <swboyd@chromium.org>, <agross@kernel.org>,
<andersson@kernel.org>, <broonie@kernel.org>,
<konrad.dybcio@somainline.org>,
<krzysztof.kozlowski+dt@linaro.org>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <mturquette@baylibre.com>,
<quic_plai@quicinc.com>, <quic_rohkumar@quicinc.com>,
<robh+dt@kernel.org>
Subject: Re: [RESEND v3 4/4] clk: qcom: lpasscc-sc7280: Add resets for audioreach
Date: Thu, 12 Jan 2023 13:23:23 +0530 [thread overview]
Message-ID: <6cea0a3f-08de-47d5-99d1-74b0d8c7b732@quicinc.com> (raw)
In-Reply-To: <CAE-0n51AZCa9K_uY=ikTLqV-g_MsSA6Lv=Zq1LMrF-wVhR8_pg@mail.gmail.com>
On 1/12/2023 2:54 AM, Stephen Boyd wrote:
Thanks for your time Stephen!!!
> Quoting Srinivasa Rao Mandadapu (2023-01-04 08:21:37)
>> The clock gating control for TX/RX/WSA core bus clocks would be required
>> to be reset(moved from hardware control) from audio core driver. Thus
>> add the support for the reset clocks in audioreach based clock driver.
>>
>> Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
>> Tested-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com>
>> ---
>> drivers/clk/qcom/lpasscc-sc7280.c | 23 +++++++++++++++++++++++
>> 1 file changed, 23 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/lpasscc-sc7280.c b/drivers/clk/qcom/lpasscc-sc7280.c
>> index 85dd5b9..1efb72d 100644
>> --- a/drivers/clk/qcom/lpasscc-sc7280.c
>> +++ b/drivers/clk/qcom/lpasscc-sc7280.c
>> @@ -12,10 +12,12 @@
>> #include <linux/regmap.h>
>>
>> #include <dt-bindings/clock/qcom,lpass-sc7280.h>
>> +#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
>>
>> #include "clk-regmap.h"
>> #include "clk-branch.h"
>> #include "common.h"
>> +#include "reset.h"
>>
>> static struct clk_branch lpass_top_cc_lpi_q6_axim_hs_clk = {
>> .halt_reg = 0x0,
>> @@ -102,6 +104,18 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sc7280_desc = {
>> .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sc7280_clocks),
>> };
>>
>> +static const struct qcom_reset_map lpass_cc_sc7280_resets[] = {
>> + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 },
>> + [LPASS_AUDIO_SWR_TX_CGCR] = { 0xa8, 1 },
>> + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
> Why are we adding these resets again? These are already exposed in
> lpassaudiocc-sc7280.c
As explained in previous versions, legacy path nodes are not being used
in ADSP based platforms, due to conflicts.
Hence lpasscc node alone being used exclusively in ADSP based solution,
resets are added.
In probe also, these reset controls are enabled based on
"qcom,adsp-pil-mode" property.
next prev parent reply other threads:[~2023-01-12 7:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-04 16:21 [RESEND v3 0/4] Add resets for ADSP based audio clock controller driver Srinivasa Rao Mandadapu
2023-01-04 16:21 ` [RESEND v3 1/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property Srinivasa Rao Mandadapu
2023-01-10 10:55 ` Krzysztof Kozlowski
2023-01-11 21:19 ` Stephen Boyd
2023-01-04 16:21 ` [RESEND v3 2/4] dt-bindings: clock: qcom,sc7280-lpasscc: Add resets for audioreach Srinivasa Rao Mandadapu
2023-01-10 10:55 ` Krzysztof Kozlowski
2023-01-04 16:21 ` [RESEND v3 3/4] clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration Srinivasa Rao Mandadapu
2023-01-11 21:22 ` Stephen Boyd
2023-01-04 16:21 ` [RESEND v3 4/4] clk: qcom: lpasscc-sc7280: Add resets for audioreach Srinivasa Rao Mandadapu
2023-01-11 21:24 ` Stephen Boyd
2023-01-12 7:53 ` Srinivasa Rao Mandadapu [this message]
2023-01-12 19:35 ` Stephen Boyd
2023-01-19 6:02 ` Srinivasa Rao Mandadapu
-- strict thread matches above, loose matches on Subject: below --
2023-01-04 15:58 [RESEND v3 0/4] Add resets for ADSP based audio clock controller driver Srinivasa Rao Mandadapu
2023-01-04 15:58 ` [RESEND v3 4/4] clk: qcom: lpasscc-sc7280: Add resets for audioreach Srinivasa Rao Mandadapu
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