[PATCH v2] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[PATCH v2] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Xilin Wu]

The GPU SMMU interrupt list includes PMU interrupts as the first two
context fault interrupts. This makes the driver register context fault
handlers on the wrong IRQs, leaving translation faults unhandled and
potentially stalling the GPU and preventing recovery.

Replace the context interrupt list with SPIs 680 through 688 and 703 in
context bank order to describe all ten hardware context interrupts.

Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
Signed-off-by: Xilin Wu <sophon@radxa.com>
---
Changes in v2:
- Describe all ten hardware context interrupts (Konrad)
- Link to v1: https://patch.msgid.link/20261013-sc8280xp-gpu-smmu-fix-v1-1-8a781e3f1554@radxa.com

To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index fbcfd3883bbb..477eb55948d5 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -3533,8 +3533,6 @@ gpu_smmu: iommu@3da0000 {
 			#global-interrupts = <2>;
 			interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
@@ -3544,7 +3542,7 @@ gpu_smmu: iommu@3da0000 {
 				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
-				     <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>;
+				     <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>;
 
 			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
 				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,

---
base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a
change-id: 20261013-sc8280xp-gpu-smmu-fix-e07e4a2ed7b2

Best regards,
--  
Xilin Wu <sophon@radxa.com>

Re: [PATCH v2] arm64: dts: qcom: sc8280xp: Fix GPU SMMU context fault interrupts

[Konrad Dybcio]

On 10/14/26 11:27 AM, Xilin Wu wrote:
> The GPU SMMU interrupt list includes PMU interrupts as the first two
> context fault interrupts. This makes the driver register context fault
> handlers on the wrong IRQs, leaving translation faults unhandled and
> potentially stalling the GPU and preventing recovery.
> 
> Replace the context interrupt list with SPIs 680 through 688 and 703 in
> context bank order to describe all ten hardware context interrupts.
> 
> Fixes: eec51ab2fd6f ("arm64: dts: qcom: sc8280xp: Add GPU related nodes")
> Signed-off-by: Xilin Wu <sophon@radxa.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad