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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: neil.armstrong@linaro.org, Bjorn Andersson <andersson@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Taniya Das <quic_tdas@quicinc.com>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 2/3] clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE_PARENT flag
Date: Wed, 17 Jul 2024 11:51:49 +0200	[thread overview]
Message-ID: <6e770e3d-b1e1-4ecb-a14e-9e909fa8a8e6@linaro.org> (raw)
In-Reply-To: <CAA8EJpomVKiVrRxSEJmjvNXLGGKVvcr2wGWtE129eUoUfgYC4g@mail.gmail.com>

On 17.07.2024 11:49 AM, Dmitry Baryshkov wrote:
> On Wed, 17 Jul 2024 at 12:47, Konrad Dybcio <konrad.dybcio@linaro.org> wrote:
>>
>> On 16.07.2024 6:46 PM, Dmitry Baryshkov wrote:
>>> On Tue, Jul 16, 2024 at 03:46:24PM GMT, neil.armstrong@linaro.org wrote:
>>>> On 16/07/2024 15:44, Dmitry Baryshkov wrote:
>>>>> On Tue, 16 Jul 2024 at 15:32, Neil Armstrong <neil.armstrong@linaro.org> wrote:
>>>>>>
>>>>>> On 16/07/2024 13:20, Dmitry Baryshkov wrote:
>>>>>>> On Tue, Jul 16, 2024 at 11:05:22AM GMT, Neil Armstrong wrote:
>>>>>>>> Add the missing CLK_SET_RATE_PARENT for the byte0_div_clk_src
>>>>>>>> and byte1_div_clk_src, the clock rate should propagate to
>>>>>>>> the corresponding _clk_src.
>>>>>>>>
>>>>>>>> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver")
>>>>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>>>>>>>> ---
>>>>>>>>    drivers/clk/qcom/dispcc-sm8650.c | 2 ++
>>>>>>>>    1 file changed, 2 insertions(+)
>>>>>>>
>>>>>>> This doesn't seem correct, the byte1_div_clk_src is a divisor, so the
>>>>>>> rate should not be propagated. Other platforms don't set this flag.
>>>>>>>
>>>>>>
>>>>>> Why not ? the disp_cc_mdss_byte1_clk_src has CLK_SET_RATE_PARENT and a div_table,
>>>>>> and we only pass DISP_CC_MDSS_BYTE1_CLK to the dsi controller.
>>>>>
>>>>> Yes, the driver sets byte_clk with the proper rate, then it sets
>>>>> byte_intf_clk, which results in a proper divisor.
>>>>> If we have CLK_SET_RATE_PARENT for byte1_div_clk_src, then setting
>>>>> byte_intf_clk rate will also result in a rate change for the byte_clk
>>>>> rate.
>>>>>
>>>>> Note, all other platforms don't set that flag for this reason (I think
>>>>> I had to remove it during sm8450 development for this reason).
>>>>>
>>>>
>>>> Ack, I think this deserves a comment explaining this, I'll add it.
>>>
>>> But where to place it? This applies to _all_ dispcc controllers.
>>
>> Commit message
> 
> It is already committed.

You can mention in it the message of this patch.

Konrad

  reply	other threads:[~2024-07-17  9:51 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-16  9:05 [PATCH v3 0/3] clk: qcom: dispcc-sm8650: round of fixes Neil Armstrong
2024-07-16  9:05 ` [PATCH v3 1/3] clk: qcom: dispcc-sm8650: Park RCG's clk source at XO during disable Neil Armstrong
2024-07-16 10:38   ` Konrad Dybcio
2024-07-16 11:40   ` Dmitry Baryshkov
2024-07-16 12:27     ` Neil Armstrong
2024-07-16  9:05 ` [PATCH v3 2/3] clk: qcom: dispcc-sm8650: add missing CLK_SET_RATE_PARENT flag Neil Armstrong
2024-07-16 11:20   ` Dmitry Baryshkov
2024-07-16 12:32     ` Neil Armstrong
2024-07-16 13:44       ` Dmitry Baryshkov
2024-07-16 13:46         ` neil.armstrong
2024-07-16 16:46           ` Dmitry Baryshkov
2024-07-17  9:47             ` Konrad Dybcio
2024-07-17  9:49               ` Dmitry Baryshkov
2024-07-17  9:51                 ` Konrad Dybcio [this message]
2024-07-17  9:53                 ` neil.armstrong
2024-07-17  9:57                   ` Dmitry Baryshkov
2024-07-17 10:13                     ` Konrad Dybcio
2024-07-16  9:05 ` [PATCH v3 3/3] clk: qcom: dispcc-sm8650: Update the GDSC flags Neil Armstrong

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