[PATCH 0/2] Enable ethernet on qcs615

[PATCH 0/2] Enable ethernet on qcs615

[Yijie Yang]

Add dts nodes to enable ethernet interface on qcs615-ride platforms.
This platform operates with RGMII interface and lacks SerDes. The EMAC and
EPHY version are the same as those in sm8150.

Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
---
This patch series depends on below patch series:
https://lore.kernel.org/all/20240926-add_initial_support_for_qcs615-v3-0-e37617e91c62@quicinc.com/
https://lore.kernel.org/all/20241010-schema-v1-0-98b2d0a2f7a2@quicinc.com/

---
Yijie Yang (2):
      arm64: dts: qcom: qcs615: add ethernet node
      arm64: dts: qcom: qcs615-ride: Enable ethernet node

 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 105 +++++++++++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/qcs615.dtsi     |  27 ++++++++
 2 files changed, 132 insertions(+)
---
base-commit: 70c6ab36f8b7756260369952a3c13b3362034bd1
change-id: 20241010-dts_qcs615-d7fa4bc599e9

Best regards,
-- 
Yijie Yang <quic_yijiyang@quicinc.com>

[PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node

[Yijie Yang]

Add ethqos ethernet controller node for QCS615 SoC.

Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
index 0d8fb557cf48..ba737cd89679 100644
--- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
@@ -420,6 +420,33 @@ soc: soc@0 {
 		#address-cells = <2>;
 		#size-cells = <2>;
 
+		ethernet: ethernet@20000 {
+			compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos";
+			reg = <0x0 0x20000 0x0 0x10000>,
+			      <0x0 0x36000 0x0 0x100>;
+			reg-names = "stmmaceth", "rgmii";
+
+			clocks = <&gcc GCC_EMAC_AXI_CLK>,
+			         <&gcc GCC_EMAC_SLV_AHB_CLK>,
+			         <&gcc GCC_EMAC_PTP_CLK>,
+			         <&gcc GCC_EMAC_RGMII_CLK>;
+			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
+
+			interrupts = <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+			             <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq", "eth_lpi";
+
+			power-domains = <&gcc EMAC_GDSC>;
+			iommus = <&apps_smmu 0x1c0 0x0>;
+
+			snps,tso;
+			snps,pbl = <32>;
+			rx-fifo-depth = <16384>;
+			tx-fifo-depth = <20480>;
+
+			status = "disabled";
+		};
+
 		gcc: clock-controller@100000 {
 			compatible = "qcom,qcs615-gcc";
 			reg = <0 0x00100000 0 0x1f0000>;

-- 
2.34.1

Re: [PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node

[Konrad Dybcio]

On 10.10.2024 5:05 AM, Yijie Yang wrote:
> Add ethqos ethernet controller node for QCS615 SoC.
> 
> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> index 0d8fb557cf48..ba737cd89679 100644
> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
> @@ -420,6 +420,33 @@ soc: soc@0 {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
>  
> +		ethernet: ethernet@20000 {
> +			compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos";
> +			reg = <0x0 0x20000 0x0 0x10000>,
> +			      <0x0 0x36000 0x0 0x100>;

Please pad the address part to 8 hex digits with leading zeroes

> +			reg-names = "stmmaceth", "rgmii";
> +
> +			clocks = <&gcc GCC_EMAC_AXI_CLK>,
> +			         <&gcc GCC_EMAC_SLV_AHB_CLK>,
> +			         <&gcc GCC_EMAC_PTP_CLK>,
> +			         <&gcc GCC_EMAC_RGMII_CLK>;
> +			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";

Please make this a vertical list, just like clocks

Konrad

Re: [PATCH 1/2] arm64: dts: qcom: qcs615: add ethernet node

[Yijie Yang]

On 2024-11-16 03:11, Konrad Dybcio wrote:
> On 10.10.2024 5:05 AM, Yijie Yang wrote:
>> Add ethqos ethernet controller node for QCS615 SoC.
>>
>> Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/qcs615.dtsi | 27 +++++++++++++++++++++++++++
>>   1 file changed, 27 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/qcs615.dtsi b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> index 0d8fb557cf48..ba737cd89679 100644
>> --- a/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/qcs615.dtsi
>> @@ -420,6 +420,33 @@ soc: soc@0 {
>>   		#address-cells = <2>;
>>   		#size-cells = <2>;
>>   
>> +		ethernet: ethernet@20000 {
>> +			compatible = "qcom,qcs615-ethqos", "qcom,sm8150-ethqos";
>> +			reg = <0x0 0x20000 0x0 0x10000>,
>> +			      <0x0 0x36000 0x0 0x100>;
> 
> Please pad the address part to 8 hex digits with leading zeroes
> 
>> +			reg-names = "stmmaceth", "rgmii";
>> +
>> +			clocks = <&gcc GCC_EMAC_AXI_CLK>,
>> +			         <&gcc GCC_EMAC_SLV_AHB_CLK>,
>> +			         <&gcc GCC_EMAC_PTP_CLK>,
>> +			         <&gcc GCC_EMAC_RGMII_CLK>;
>> +			clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii";
> 
> Please make this a vertical list, just like clocks

Sure, I will revise.

> 
> Konrad

-- 
Best Regards,
Yijie

[PATCH 2/2] arm64: dts: qcom: qcs615-ride: Enable ethernet node

[Yijie Yang]

Enable the ethernet node, add the phy node and pinctrl for ethernet.

Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
---
 arch/arm64/boot/dts/qcom/qcs615-ride.dts | 105 +++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
index 538e697e2dac..3d3c9edd860b 100644
--- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts
+++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts
@@ -5,6 +5,7 @@
 /dts-v1/;
 
 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
+#include <dt-bindings/gpio/gpio.h>
 #include "qcs615.dtsi"
 #include "qcs615-pmic.dtsi"
 
@@ -201,6 +202,60 @@ vreg_l17a: ldo17 {
 	};
 };
 
+&ethernet {
+	status = "okay";
+
+	pinctrl-0 = <&ethernet_defaults>;
+	pinctrl-names = "default";
+
+	phy-handle = <&rgmii_phy>;
+	phy-mode = "rgmii";
+	max-speed = <1000>;
+
+	snps,mtl-rx-config = <&mtl_rx_setup>;
+	snps,mtl-tx-config = <&mtl_tx_setup>;
+
+	mdio: mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		rgmii_phy: phy@7 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0x7>;
+
+			interrupts-extended = <&tlmm 121 IRQ_TYPE_EDGE_FALLING>;
+			device_type = "ethernet-phy";
+			reset-gpios = <&tlmm 104 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <11000>;
+			reset-deassert-us = <70000>;
+		};
+	};
+
+	mtl_rx_setup: rx-queues-config {
+		snps,rx-queues-to-use = <1>;
+		snps,rx-sched-sp;
+
+		queue0 {
+			snps,dcb-algorithm;
+			snps,map-to-dma-channel = <0x0>;
+			snps,route-up;
+			snps,priority = <0x1>;
+		};
+	};
+
+	mtl_tx_setup: tx-queues-config {
+		snps,tx-queues-to-use = <1>;
+		snps,tx-sched-wrr;
+
+		queue0 {
+			snps,weight = <0x10>;
+			snps,dcb-algorithm;
+			snps,priority = <0x0>;
+		};
+	};
+};
+
 &gcc {
 	clocks = <&rpmhcc RPMH_CXO_CLK>,
 		 <&rpmhcc RPMH_CXO_CLK_A>,
@@ -292,6 +347,56 @@ &mdss_dsi0_phy {
 	vdds-supply = <&vreg_l5a>;
 };
 
+&tlmm {
+	ethernet_defaults: ethernet-defaults-state {
+		mdc-pins {
+			pins = "gpio113";
+			function = "rgmii";
+			bias-pull-up;
+		};
+
+		mdio-pins {
+			pins = "gpio114";
+			function = "rgmii";
+			bias-pull-up;
+		};
+
+		rgmii-rx-pins {
+			pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112";
+			function = "rgmii";
+			bias-disable;
+			drive-strength = <2>;
+		};
+
+		rgmii-tx-pins {
+			pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97";
+			function = "rgmii";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+
+		phy-intr-pins {
+			pins = "gpio121";
+			function = "gpio";
+			bias-disable;
+			drive-strength = <8>;
+		};
+
+		pps-pins {
+			pins = "gpio91";
+			function = "rgmii";
+			bias-disable;
+			drive-strength = <8>;
+		};
+
+		phy-reset-pins {
+			pins = "gpio104";
+			function = "gpio";
+			bias-pull-up;
+			drive-strength = <16>;
+		};
+	};
+};
 
 &tlmm {
 	ioexp_intr_active: ioexp_intr_active {

-- 
2.34.1