From: Krzysztof Kozlowski <krzk@kernel.org>
To: Judith Mendez <jm@ti.com>, Nishanth Menon <nm@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
Ulf Hansson <ulf.hansson@linaro.org>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
Santosh Shilimkar <ssantosh@kernel.org>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org
Subject: Re: [PATCH 1/4] dt-bindings: hwinfo: Add second register range for GP_SW
Date: Thu, 7 Aug 2025 10:22:19 +0200 [thread overview]
Message-ID: <736f09e0-075a-48e0-9b32-6b8805a7ee2a@kernel.org> (raw)
In-Reply-To: <e9394117-996c-4134-b9f2-50accf633601@ti.com>
On 06/08/2025 17:24, Judith Mendez wrote:
> Hi Krystoff,
That's not really my name. I know it is tricky to type, so it's enough
to say Hi.
>>>
>>> reg:
>>> - maxItems: 1
>>> + maxItems: 2
>>> + minItems: 1
>>
>> They always come with reversed order... but anyway, you instead must
>> list the items with minItems.
>>
>> another problem is that this is not supposed to be per register. I
>> already complained more than once about some of TI bindings: stop
>> creating device nodes or address spaces per register.
>>
>> That's one address space.
>
> That does not really make sense. Registers jtag vs gp_sw have a
> different back-end, one from silicon and another from efuse. Not even
How does the datasheet describe this address space(s) (not registers,
address space)?
> sure if the memory map will always be the same across processors.
>
>>
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-08-07 8:22 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-05 23:49 [PATCH 0/4] Add support for AM62P SR1.2 Judith Mendez
2025-08-05 23:49 ` [PATCH 1/4] dt-bindings: hwinfo: Add second register range for GP_SW Judith Mendez
2025-08-06 6:40 ` Krzysztof Kozlowski
2025-08-06 15:24 ` Judith Mendez
2025-08-07 8:22 ` Krzysztof Kozlowski [this message]
2025-08-05 23:49 ` [PATCH 2/4] soc: ti: k3-socinfo: Add support for AM62P variants Judith Mendez
2025-08-07 17:24 ` Andrew Davis
2025-08-07 22:29 ` Judith Mendez
2025-08-05 23:49 ` [PATCH 3/4] mmc: sdhci_am654: Disable HS400 for AM62P SR1.0 and SR1.1 Judith Mendez
2025-08-07 17:28 ` Andrew Davis
2025-08-07 22:14 ` Judith Mendez
2025-08-05 23:49 ` [PATCH 4/4] arm64: dts: ti: k3-am62p-j722s-common-wakeup: Add GP_SW reg range to chipid node Judith Mendez
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