* [PATCH v3 1/4] arm64: dts: qcom: nord: Add the USB controller nodes
2026-10-13 11:34 [PATCH v3 0/4] arm64: dts: qcom: nord: Add USB support Bartosz Golaszewski
@ 2026-10-13 11:34 ` Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 2/4] arm64: dts: qcom: nord-embedded: Add USB resources and PHYs Bartosz Golaszewski
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Bartosz Golaszewski @ 2026-10-13 11:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski,
Abel Vesa, Konrad Dybcio
Add the base nodes for the three DWC3 USB controllers. These carry only
the SoC-invariant properties and are disabled by default. The extension
for the embedded Nord variant and relevant board files will add the
platform resources and enable them.
USB_2 has no SuperSpeed PHY and no 'ss_phy_irq' on this SoC, so it is
capped to high-speed and told to use UTMI as its pipe clock.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord.dtsi | 100 +++++++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
index aa52238adb98046ec36a88c7f277dde34582aeb0..4f1908f765cb026602203b473142317008738606 100644
--- a/arch/arm64/boot/dts/qcom/nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord.dtsi
@@ -1742,6 +1742,106 @@ ipcc0: mailbox@9007000 {
#mbox-cells = <2>;
};
+ usb_2: usb@a200000 {
+ compatible = "qcom,nord-dwc3",
+ "qcom,snps-dwc3";
+ reg = <0x0 0x0a200000 0x0 0xfc100>;
+
+ interrupts-extended = <&intc GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 8 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 7 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ iommus = <&apps_smmu_0 0x14e0 0x0>;
+
+ dma-coherent;
+ wakeup-source;
+ usb-role-switch;
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ qcom,select-utmi-as-pipe-clk;
+
+ maximum-speed = "high-speed";
+
+ status = "disabled";
+ };
+
+ usb_1: usb@a400000 {
+ compatible = "qcom,nord-dwc3",
+ "qcom,snps-dwc3";
+ reg = <0x0 0x0a400000 0x0 0xfc100>;
+
+ interrupts-extended = <&intc GIC_SPI 917 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 918 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 919 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 13 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 41 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ iommus = <&apps_smmu_0 0x15c0 0x0>;
+
+ dma-coherent;
+ wakeup-source;
+ usb-role-switch;
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+
+ status = "disabled";
+ };
+
+ usb_0: usb@a600000 {
+ compatible = "qcom,nord-dwc3",
+ "qcom,snps-dwc3";
+ reg = <0x0 0x0a600000 0x0 0xfc100>;
+
+ interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dwc_usb3",
+ "pwr_event",
+ "hs_phy_irq",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ iommus = <&apps_smmu_0 0x1500 0x0>;
+
+ dma-coherent;
+ wakeup-source;
+ usb-role-switch;
+
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+
+ status = "disabled";
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,nord-pdc",
"qcom,pdc";
--
2.47.3
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 2/4] arm64: dts: qcom: nord-embedded: Add USB resources and PHYs
2026-10-13 11:34 [PATCH v3 0/4] arm64: dts: qcom: nord: Add USB support Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 1/4] arm64: dts: qcom: nord: Add the USB controller nodes Bartosz Golaszewski
@ 2026-10-13 11:34 ` Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 3/4] arm64: dts: qcom: nord-rrd: Enable USB ports Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: " Bartosz Golaszewski
3 siblings, 0 replies; 7+ messages in thread
From: Bartosz Golaszewski @ 2026-10-13 11:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski,
Abel Vesa, Konrad Dybcio
Add the platform resources for the three USB controllers on the embedded
Nord variant: clocks, resets, power domains and interconnect paths.
Add the eUSB2 PHY for each of the three controllers, plus the QMP combo
PHYs for USB_0 and USB_1, and feed the two QMP USB3 pipe clocks back
into negcc, which so far carried placeholder zeros in their place.
The eUSB2 PHY of instance 2 gets no 'resets': the SoC provides only two
QUSB2PHY block resets, belonging to instances 0 and 1. Instance 2 comes
out of reset with the rest of the USB20 tile, driven by the controller.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Co-developed-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 311 +++++++++++++++++++++++++++-
1 file changed, 309 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index 6dc4c871f41e065fd193fdf552d062c91343da28..7db113e05897db05cafeb509f039eedc19f54444 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,nord-rpmh.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -857,6 +858,161 @@ hpass_ag_noc: interconnect@5fc0000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
+ usb_2_hsphy: phy@88e0000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088e0000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_2_CLKREF_EN>,
+ <&negcc NE_GCC_AHB2PHY_CLK>;
+ clock-names = "ref",
+ "bus";
+
+ resets = <&negcc NE_GCC_QUSB2PHY_PRIM_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_0_qmpphy: phy@88e1000 {
+ compatible = "qcom,nord-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e1000 0x0 0x3000>;
+
+ clocks = <&negcc NE_GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_0_CLKREF_EN>,
+ <&negcc NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&negcc NE_GCC_USB3_PRIM_PHY_PIPE_CLK>,
+ <&negcc NE_GCC_AHB2PHY_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "cfg_ahb";
+
+ power-domains = <&negcc NE_GCC_USB3_PHY_GDSC>;
+
+ resets = <&negcc NE_GCC_USB3_PHY_PRIM_BCR>,
+ <&negcc NE_GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_0_qmpphy_usb_ss_out: endpoint@1 {
+ reg = <1>;
+ data-lanes = <1 0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_0_dwc3_ss>;
+ };
+ };
+ };
+ };
+
+ usb_1_qmpphy: phy@88e4000 {
+ compatible = "qcom,nord-qmp-usb3-dp-phy";
+ reg = <0x0 0x088e4000 0x0 0x3000>;
+
+ clocks = <&negcc NE_GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&tcsrcc TCSR_USB3_1_CLKREF_EN>,
+ <&negcc NE_GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&negcc NE_GCC_USB3_SEC_PHY_PIPE_CLK>,
+ <&negcc NE_GCC_AHB2PHY_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe",
+ "cfg_ahb";
+
+ power-domains = <&negcc NE_GCC_USB3_SEC_PHY_GDSC>;
+
+ resets = <&negcc NE_GCC_USB3_PHY_SEC_BCR>,
+ <&negcc NE_GCC_USB3_DP_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_1_qmpphy_usb_ss_out: endpoint@1 {
+ reg = <1>;
+ data-lanes = <1 0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_qmpphy_usb_ss_in: endpoint {
+ remote-endpoint = <&usb_1_dwc3_ss>;
+ };
+ };
+ };
+ };
+
+ usb_0_hsphy: phy@88ea000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088ea000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_0_CLKREF_EN>,
+ <&negcc NE_GCC_AHB2PHY_CLK>;
+ clock-names = "ref",
+ "bus";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ usb_1_hsphy: phy@88eb000 {
+ compatible = "qcom,nord-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0x0 0x088eb000 0x0 0x154>;
+
+ clocks = <&tcsrcc TCSR_USB2_1_CLKREF_EN>,
+ <&negcc NE_GCC_AHB2PHY_CLK>;
+ clock-names = "ref",
+ "bus";
+
+ resets = <&negcc NE_GCC_QUSB2PHY_SEC_BCR>;
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
negcc: clock-controller@8900000 {
compatible = "qcom,nord-negcc";
reg = <0x0 0x08900000 0x0 0xf4200>;
@@ -865,8 +1021,8 @@ negcc: clock-controller@8900000 {
<0>,
<0>,
<0>,
- <0>,
- <0>;
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -1989,3 +2145,154 @@ opp-403000000 {
};
};
};
+
+&usb_0 {
+ clocks = <&negcc NE_GCC_CNOC_USB3_PRIM_AXI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_SLEEP_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB3_0_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB31_PRIM_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB31_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&negcc NE_GCC_USB31_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB31_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_0_hsphy>,
+ <&usb_0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_1 {
+ clocks = <&negcc NE_GCC_CNOC_USB3_SEC_AXI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_SLEEP_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB3_1_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB31_SEC_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB31_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ power-domains = <&negcc NE_GCC_USB31_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB31_SEC_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_1_hsphy>,
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_dwc3_hs: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_dwc3_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_in>;
+ };
+ };
+ };
+};
+
+&usb_2 {
+ clocks = <&negcc NE_GCC_CNOC_USB2_AXI_CLK>,
+ <&negcc NE_GCC_USB20_MASTER_CLK>,
+ <&negcc NE_GCC_AGGRE_NOC_USB2_AXI_CLK>,
+ <&negcc NE_GCC_USB20_SLEEP_CLK>,
+ <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>,
+ <&tcsrcc TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "xo";
+
+ assigned-clocks = <&negcc NE_GCC_USB20_MOCK_UTMI_CLK>,
+ <&negcc NE_GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <120000000>;
+
+ power-domains = <&negcc NE_GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&negcc NE_GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&aggre1_noc_tile MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+
+ port {
+ usb_2_dwc3_hs: endpoint {
+ };
+ };
+};
--
2.47.3
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 3/4] arm64: dts: qcom: nord-rrd: Enable USB ports
2026-10-13 11:34 [PATCH v3 0/4] arm64: dts: qcom: nord: Add USB support Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 1/4] arm64: dts: qcom: nord: Add the USB controller nodes Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 2/4] arm64: dts: qcom: nord-embedded: Add USB resources and PHYs Bartosz Golaszewski
@ 2026-10-13 11:34 ` Bartosz Golaszewski
2026-10-13 11:34 ` [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: " Bartosz Golaszewski
3 siblings, 0 replies; 7+ messages in thread
From: Bartosz Golaszewski @ 2026-10-13 11:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski,
Abel Vesa, Dmitry Baryshkov, Konrad Dybcio
From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Describe the RRD USB topology. Enable i2c9 and add the two NXP PTN3222
eUSB2 repeaters for USB_0 and USB_1, supplied from vreg_l3l_1p8 and a new
fixed 3.3 V pre-regulator, and reset through pmau0102_i GPIOs 9 and 10.
Add the onsemi FUSB15201 Type-C controller at 0x50 with its interrupt and
pinctrl state on pmau0102_i gpio8. Unlike RIDE, only port A of
the controller is wired on this board, to USB_0, so a single
usb-c-connector is described and port B is left out. USB_0 is configured
for OTG with usb-role-switch and its HS and SS endpoints are linked to
the dwc3 HS endpoint and the QMP combo PHY SS output.
USB_1 is a fixed host port feeding an on-board Genesys Logic GL3590 USB
3.1 hub. Add the HS and SS hub pair as children of USB_1, linked with
peer-hub, with the HS half reset via TLMM GPIO 170 and the SS half
additionally supplied by a fixed 1.2 V rail.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-rrd.dts | 166 ++++++++++++++++++++++++++++++++++
1 file changed, 166 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-rrd.dts b/arch/arm64/boot/dts/qcom/nord-rrd.dts
index 47978df0af92dbba7303dd38ede201725c0347e2..3965042f4712bb4d406b53c81464100c7db86de3 100644
--- a/arch/arm64/boot/dts/qcom/nord-rrd.dts
+++ b/arch/arm64/boot/dts/qcom/nord-rrd.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "nord-embedded.dtsi"
@@ -53,6 +54,22 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ vreg_hub_1p2: regulator-hub-1p2 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_hub_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ vreg_per_3p3: regulator-per-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_per_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
};
&apps_rsc {
@@ -377,6 +394,86 @@ rtc@32 {
};
};
+&i2c9 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ usb0_repeater: redriver@43 {
+ compatible = "nxp,ptn3222";
+ reg = <0x43>;
+ #phy-cells = <0>;
+ vdd1v8-supply = <&vreg_l3l_1p8>;
+ vdd3v3-supply = <&vreg_per_3p3>;
+ reset-gpios = <&pmau0102_i_gpios 9 GPIO_ACTIVE_LOW>;
+ };
+
+ usb1_repeater: redriver@4f {
+ compatible = "nxp,ptn3222";
+ reg = <0x4f>;
+ #phy-cells = <0>;
+ vdd1v8-supply = <&vreg_l3l_1p8>;
+ vdd3v3-supply = <&vreg_per_3p3>;
+ reset-gpios = <&pmau0102_i_gpios 10 GPIO_ACTIVE_LOW>;
+ };
+
+ typec@50 {
+ compatible = "onnn,fusb15201";
+ reg = <0x50>;
+ interrupts-extended = <&pmau0102_i_gpios 8 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&usb_pd_int_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /*
+ * Only port A of the controller is wired up on this board, to
+ * USB_0. Port B is left unconnected.
+ */
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ label = "USB-C0";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_con_hs: endpoint {
+ remote-endpoint = <&usb_0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_con_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&pmau0102_i_gpios {
+ usb_pd_int_default: usb-pd-int-state {
+ pins = "gpio8";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+};
+
&qupv3_0 {
firmware-name = "qcom/nord/qupv3fw.elf";
@@ -459,3 +556,72 @@ &ufs_mem_phy {
status = "okay";
};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_0_dwc3_hs {
+ remote-endpoint = <&usb_0_con_hs>;
+};
+
+&usb_0_hsphy {
+ vdd-supply = <&vreg_l1h_0p9>;
+ vdda12-supply = <&vreg_l2h_1p2>;
+
+ phys = <&usb0_repeater>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy {
+ vdda-phy-supply = <&vreg_l2k_0p9>;
+ vdda-pll-supply = <&vreg_l2h_1p2>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy_usb_ss_out {
+ remote-endpoint = <&usb_0_con_ss>;
+};
+
+&usb_1 {
+ dr_mode = "host";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "okay";
+
+ hub_hs: hub@1 {
+ compatible = "usb5e3,610";
+ reg = <1>;
+ reset-gpios = <&tlmm 170 GPIO_ACTIVE_LOW>;
+ vdd-supply = <&vreg_per_3p3>;
+ peer-hub = <&hub_ss>;
+ };
+
+ hub_ss: hub@2 {
+ compatible = "usb5e3,625";
+ reg = <2>;
+ vdd-supply = <&vreg_per_3p3>;
+ vdd12-supply = <&vreg_hub_1p2>;
+ peer-hub = <&hub_hs>;
+ };
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1h_0p9>;
+ vdda12-supply = <&vreg_l2h_1p2>;
+
+ phys = <&usb1_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l2k_0p9>;
+ vdda-pll-supply = <&vreg_l2h_1p2>;
+
+ status = "okay";
+};
--
2.47.3
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: Enable USB ports
2026-10-13 11:34 [PATCH v3 0/4] arm64: dts: qcom: nord: Add USB support Bartosz Golaszewski
` (2 preceding siblings ...)
2026-10-13 11:34 ` [PATCH v3 3/4] arm64: dts: qcom: nord-rrd: Enable USB ports Bartosz Golaszewski
@ 2026-10-13 11:34 ` Bartosz Golaszewski
2026-10-13 19:32 ` Dmitry Baryshkov
2026-10-22 9:05 ` Konrad Dybcio
3 siblings, 2 replies; 7+ messages in thread
From: Bartosz Golaszewski @ 2026-10-13 11:34 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl
Cc: linux-arm-msm, devicetree, linux-kernel, Bartosz Golaszewski, Abel Vesa
From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Wire up the board specific pieces for USB ports. Enable i2c9 and add the
three NXP PTN3222 eUSB2 repeaters (one per USB port) with their 1.8 V
supply and reset GPIOs on the PMIC GPIO expanders.
Add the onsemi FUSB15201 dual port Type-C controller at 0x50, with
its interrupt and pinctrl state on pmau0102_i gpio8. Both controller
ports are wired on this board, so describe two usb-c-connector
children and cross-link their HS and SS endpoints to the dwc3 HS
endpoint and the QMP combo PHY SS output of USB_0 and USB_1. Both
controllers therefore run in OTG mode with usb-role-switch.
USB_2 has no Type-C connector, so it is configured as a fixed host
port. Its VBUS is supplied by a fixed regulator gated by
pmau0102_h gpio3, kept always-on since nothing switches it at
runtime.
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/nord-ride-embedded.dts | 222 ++++++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
index 49635695f832eca91040e45bcd75eebd7d566906..cd73ad19b368ee04e512b9ba63bd4336d80ba4d1 100644
--- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
+++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "nord-embedded.dtsi"
@@ -53,6 +54,37 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ vreg_per_3p3: regulator-per-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vreg_per_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usb2_vbus: regulator-usb2-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb2_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pmau0102_h_gpios 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ usb2-connector {
+ compatible = "usb-a-connector";
+ label = "USB-2-Type-A";
+ power-role = "source";
+
+ vbus-supply = <&usb2_vbus>;
+
+ port {
+ usb2_con_hs: endpoint {
+ remote-endpoint = <&usb_2_dwc3_hs>;
+ };
+ };
+ };
};
&apps_rsc {
@@ -366,6 +398,121 @@ vreg_l3l_1p8: ldo3 {
};
};
+&i2c9 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ usb0_repeater: redriver@43 {
+ compatible = "nxp,ptn3222";
+ reg = <0x43>;
+ #phy-cells = <0>;
+ vdd1v8-supply = <&vreg_l3l_1p8>;
+ vdd3v3-supply = <&vreg_per_3p3>;
+ reset-gpios = <&pmau0102_i_gpios 9 GPIO_ACTIVE_LOW>;
+ };
+
+ usb2_repeater: redriver@47 {
+ compatible = "nxp,ptn3222";
+ reg = <0x47>;
+ #phy-cells = <0>;
+ vdd1v8-supply = <&vreg_l3l_1p8>;
+ vdd3v3-supply = <&vreg_per_3p3>;
+ reset-gpios = <&pmau0102_l_gpios 3 GPIO_ACTIVE_LOW>;
+ };
+
+ usb1_repeater: redriver@4f {
+ compatible = "nxp,ptn3222";
+ reg = <0x4f>;
+ #phy-cells = <0>;
+ vdd1v8-supply = <&vreg_l3l_1p8>;
+ vdd3v3-supply = <&vreg_per_3p3>;
+ reset-gpios = <&pmau0102_i_gpios 10 GPIO_ACTIVE_LOW>;
+ };
+
+ typec@50 {
+ compatible = "onnn,fusb15201";
+ reg = <0x50>;
+ interrupts-extended = <&pmau0102_i_gpios 8 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&usb_pd_int_default>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ connector@0 {
+ compatible = "usb-c-connector";
+ reg = <0>;
+ label = "USB-C0";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_0_con_hs: endpoint {
+ remote-endpoint = <&usb_0_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_0_con_ss: endpoint {
+ remote-endpoint = <&usb_0_qmpphy_usb_ss_out>;
+ };
+ };
+ };
+ };
+
+ connector@1 {
+ compatible = "usb-c-connector";
+ reg = <1>;
+ label = "USB-C1";
+ power-role = "dual";
+ data-role = "dual";
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ usb_1_con_hs: endpoint {
+ remote-endpoint = <&usb_1_dwc3_hs>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ usb_1_con_ss: endpoint {
+ remote-endpoint = <&usb_1_qmpphy_usb_ss_out>;
+ };
+ };
+ };
+ };
+ };
+};
+
+&pmau0102_i_gpios {
+ usb_pd_int_default: usb-pd-int-state {
+ pins = "gpio8";
+ function = "normal";
+ input-enable;
+ bias-pull-up;
+ power-source = <0>;
+ };
+};
+
&qupv3_0 {
firmware-name = "qcom/nord/qupv3fw.elf";
@@ -440,3 +587,78 @@ &ufs_mem_phy {
status = "okay";
};
+
+&usb_0 {
+ status = "okay";
+};
+
+&usb_0_dwc3_hs {
+ remote-endpoint = <&usb_0_con_hs>;
+};
+
+&usb_0_hsphy {
+ vdd-supply = <&vreg_l1h_0p9>;
+ vdda12-supply = <&vreg_l2h_1p2>;
+
+ phys = <&usb0_repeater>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy {
+ vdda-phy-supply = <&vreg_l2k_0p9>;
+ vdda-pll-supply = <&vreg_l2h_1p2>;
+
+ status = "okay";
+};
+
+&usb_0_qmpphy_usb_ss_out {
+ remote-endpoint = <&usb_0_con_ss>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3_hs {
+ remote-endpoint = <&usb_1_con_hs>;
+};
+
+&usb_1_hsphy {
+ vdd-supply = <&vreg_l1h_0p9>;
+ vdda12-supply = <&vreg_l2h_1p2>;
+
+ phys = <&usb1_repeater>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ vdda-phy-supply = <&vreg_l2k_0p9>;
+ vdda-pll-supply = <&vreg_l2h_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_qmpphy_usb_ss_out {
+ remote-endpoint = <&usb_1_con_ss>;
+};
+
+&usb_2 {
+ dr_mode = "host";
+
+ status = "okay";
+};
+
+&usb_2_dwc3_hs {
+ remote-endpoint = <&usb2_con_hs>;
+};
+
+&usb_2_hsphy {
+ vdd-supply = <&vreg_l1h_0p9>;
+ vdda12-supply = <&vreg_l2h_1p2>;
+
+ phys = <&usb2_repeater>;
+
+ status = "okay";
+};
--
2.47.3
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: Enable USB ports
2026-10-13 11:34 ` [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: " Bartosz Golaszewski
@ 2026-10-13 19:32 ` Dmitry Baryshkov
2026-10-22 9:05 ` Konrad Dybcio
1 sibling, 0 replies; 7+ messages in thread
From: Dmitry Baryshkov @ 2026-10-13 19:32 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl,
linux-arm-msm, devicetree, linux-kernel, Abel Vesa
On Tue, Oct 13, 2026 at 01:34:49PM +0200, Bartosz Golaszewski wrote:
> From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>
> Wire up the board specific pieces for USB ports. Enable i2c9 and add the
> three NXP PTN3222 eUSB2 repeaters (one per USB port) with their 1.8 V
> supply and reset GPIOs on the PMIC GPIO expanders.
>
> Add the onsemi FUSB15201 dual port Type-C controller at 0x50, with
> its interrupt and pinctrl state on pmau0102_i gpio8. Both controller
> ports are wired on this board, so describe two usb-c-connector
> children and cross-link their HS and SS endpoints to the dwc3 HS
> endpoint and the QMP combo PHY SS output of USB_0 and USB_1. Both
> controllers therefore run in OTG mode with usb-role-switch.
>
> USB_2 has no Type-C connector, so it is configured as a fixed host
> port. Its VBUS is supplied by a fixed regulator gated by
> pmau0102_h gpio3, kept always-on since nothing switches it at
> runtime.
>
> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
> Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
> Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/nord-ride-embedded.dts | 222 ++++++++++++++++++++++++
> 1 file changed, 222 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: Enable USB ports
2026-10-13 11:34 ` [PATCH v3 4/4] arm64: dts: qcom: nord-ride-embedded: " Bartosz Golaszewski
2026-10-13 19:32 ` Dmitry Baryshkov
@ 2026-10-22 9:05 ` Konrad Dybcio
1 sibling, 0 replies; 7+ messages in thread
From: Konrad Dybcio @ 2026-10-22 9:05 UTC (permalink / raw)
To: Bartosz Golaszewski, Bjorn Andersson, Konrad Dybcio, Abel Vesa,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo, brgl
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
On 10/13/26 1:34 PM, Bartosz Golaszewski wrote:
> From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
>
> Wire up the board specific pieces for USB ports. Enable i2c9 and add the
> three NXP PTN3222 eUSB2 repeaters (one per USB port) with their 1.8 V
> supply and reset GPIOs on the PMIC GPIO expanders.
>
> Add the onsemi FUSB15201 dual port Type-C controller at 0x50, with
> its interrupt and pinctrl state on pmau0102_i gpio8. Both controller
> ports are wired on this board, so describe two usb-c-connector
> children and cross-link their HS and SS endpoints to the dwc3 HS
> endpoint and the QMP combo PHY SS output of USB_0 and USB_1. Both
> controllers therefore run in OTG mode with usb-role-switch.
>
> USB_2 has no Type-C connector, so it is configured as a fixed host
> port. Its VBUS is supplied by a fixed regulator gated by
> pmau0102_h gpio3, kept always-on since nothing switches it at
> runtime.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 7+ messages in thread