From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Ayushi Makhija <quic_amakhija@quicinc.com>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org
Cc: robdclark@gmail.com, lumag@kernel.org, sean@poorly.run,
marijn.suijten@somainline.org, airlied@gmail.com,
simona@ffwll.ch, quic_rajeevny@quicinc.com,
quic_vproddut@quicinc.com, quic_jesszhan@quicinc.com
Subject: Re: [PATCH] drm/msm: update the high bitfield of certain DSI registers
Date: Wed, 30 Jul 2025 14:45:13 +0200 [thread overview]
Message-ID: <74e3836e-af29-4b5f-b644-23bdff084c78@oss.qualcomm.com> (raw)
In-Reply-To: <20250730123938.1038640-1-quic_amakhija@quicinc.com>
On 7/30/25 2:39 PM, Ayushi Makhija wrote:
> Currently, the high bitfield of certain DSI registers
> do not align with the configuration of the SWI registers
> description. This can lead to wrong programming these DSI
> registers, for example for 4k resloution where H_TOTAL is
> taking 13 bits but software is programming only 12 bits
> because of the incorrect bitmask for H_TOTAL bitfeild,
> this is causing DSI FIFO errors. To resolve this issue,
> increase the high bitfield of the DSI registers from 12 bits
> to 16 bits in dsi.xml to match the SWI register configuration.
>
> Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
> ---
> drivers/gpu/drm/msm/registers/display/dsi.xml | 28 +++++++++----------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/registers/display/dsi.xml b/drivers/gpu/drm/msm/registers/display/dsi.xml
> index 501ffc585a9f..c7a7b633d747 100644
> --- a/drivers/gpu/drm/msm/registers/display/dsi.xml
> +++ b/drivers/gpu/drm/msm/registers/display/dsi.xml
> @@ -159,28 +159,28 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
> <bitfield name="RGB_SWAP" low="12" high="14" type="dsi_rgb_swap"/>
> </reg32>
> <reg32 offset="0x00020" name="ACTIVE_H">
> - <bitfield name="START" low="0" high="11" type="uint"/>
> - <bitfield name="END" low="16" high="27" type="uint"/>
> + <bitfield name="START" low="0" high="15" type="uint"/>
> + <bitfield name="END" low="16" high="31" type="uint"/>
> </reg32>
> <reg32 offset="0x00024" name="ACTIVE_V">
> - <bitfield name="START" low="0" high="11" type="uint"/>
> - <bitfield name="END" low="16" high="27" type="uint"/>
> + <bitfield name="START" low="0" high="15" type="uint"/>
> + <bitfield name="END" low="16" high="31" type="uint"/>
> </reg32>
> <reg32 offset="0x00028" name="TOTAL">
> - <bitfield name="H_TOTAL" low="0" high="11" type="uint"/>
> - <bitfield name="V_TOTAL" low="16" high="27" type="uint"/>
> + <bitfield name="H_TOTAL" low="0" high="15" type="uint"/>
> + <bitfield name="V_TOTAL" low="16" high="31" type="uint"/>
> </reg32>
> <reg32 offset="0x0002c" name="ACTIVE_HSYNC">
> - <bitfield name="START" low="0" high="11" type="uint"/>
> - <bitfield name="END" low="16" high="27" type="uint"/>
> + <bitfield name="START" low="0" high="15" type="uint"/>
> + <bitfield name="END" low="16" high="31" type="uint"/>
> </reg32>
> <reg32 offset="0x00030" name="ACTIVE_VSYNC_HPOS">
> - <bitfield name="START" low="0" high="11" type="uint"/>
> - <bitfield name="END" low="16" high="27" type="uint"/>
> + <bitfield name="START" low="0" high="15" type="uint"/>
> + <bitfield name="END" low="16" high="31" type="uint"/>
> </reg32>
> <reg32 offset="0x00034" name="ACTIVE_VSYNC_VPOS">
FWIW looks like at least on 8280, ACTIVE_VSYNC_HPOS offset = 0x38
and HPOS doesn't exist
Konrad
next prev parent reply other threads:[~2025-07-30 12:45 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-30 12:39 Ayushi Makhija
2025-07-30 12:45 ` Konrad Dybcio [this message]
2025-07-30 13:08 ` Dmitry Baryshkov
2025-08-01 17:41 ` Dmitry Baryshkov
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