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From: "Winiarska, Iwona" <iwona.winiarska@intel.com>
To: "linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"andrew@codeconstruct.com.au" <andrew@codeconstruct.com.au>
Cc: "billy_tsai@aspeedtech.com" <billy_tsai@aspeedtech.com>
Subject: Re: [PATCH] peci: aspeed: Clear clock_divider value before setting it
Date: Thu, 18 Apr 2024 13:41:09 +0000	[thread overview]
Message-ID: <7520ac6ef7afae66f9b1636e5806ff2bfd93584d.camel@intel.com> (raw)
In-Reply-To: <7b0ef5c90138e8c1d1829de249a480709170141b.camel@codeconstruct.com.au>

On Thu, 2024-04-18 at 09:11 +0930, Andrew Jeffery wrote:
> Hi Iwona,
> 
> On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote:
> > PECI clock divider is programmed on 10:8 bits of PECI Control register.
> > Before setting a new value, clear bits read from hardware.
> > 
> > Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>
> 
> I think it would be best to add a Fixes: tag and Cc: stable in
> accordance with the stable tree rules. Are you happy to do so?

Hi!

Technically, the initial value of this register should be 0, but I've added the
clear just to be on the safe side and to not have to rely on that.
I don't think we're ever programming invalid values in the real-world scenarios,
and because of that - I don't think this is stable material.

Thanks
-Iwona

> 
> Andrew
> 

  reply	other threads:[~2024-04-18 13:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-17 13:48 Iwona Winiarska
2024-04-17 23:41 ` Andrew Jeffery
2024-04-18 13:41   ` Winiarska, Iwona [this message]
2024-04-18 23:25     ` Andrew Jeffery
2024-06-12  2:23       ` Billy Tsai

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