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From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Iwona Winiarska <iwona.winiarska@intel.com>,
	openbmc@lists.ozlabs.org,  linux-kernel@vger.kernel.org,
	linux-aspeed@lists.ozlabs.org,
	 linux-arm-kernel@lists.infradead.org
Cc: Billy Tsai <billy_tsai@aspeedtech.com>
Subject: Re: [PATCH] peci: aspeed: Clear clock_divider value before setting it
Date: Thu, 18 Apr 2024 09:11:47 +0930	[thread overview]
Message-ID: <7b0ef5c90138e8c1d1829de249a480709170141b.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20240417134849.5793-1-iwona.winiarska@intel.com>

Hi Iwona,

On Wed, 2024-04-17 at 15:48 +0200, Iwona Winiarska wrote:
> PECI clock divider is programmed on 10:8 bits of PECI Control register.
> Before setting a new value, clear bits read from hardware.
> 
> Signed-off-by: Iwona Winiarska <iwona.winiarska@intel.com>

I think it would be best to add a Fixes: tag and Cc: stable in
accordance with the stable tree rules. Are you happy to do so?

Andrew


  reply	other threads:[~2024-04-17 23:41 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-04-17 13:48 Iwona Winiarska
2024-04-17 23:41 ` Andrew Jeffery [this message]
2024-04-18 13:41   ` Winiarska, Iwona
2024-04-18 23:25     ` Andrew Jeffery
2024-06-12  2:23       ` Billy Tsai

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