From: "Naveen N Rao (AMD)" <naveen@kernel.org>
To: Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>
Cc: <linux-kernel@vger.kernel.org>, <x86@kernel.org>,
Nikunj A Dadhania <nikunj@amd.com>,
Manali Shukla <manali.shukla@amd.com>,
Bharata B Rao <bharata@amd.com>, "H. Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: [PATCH v3 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count
Date: Tue, 21 Jul 2026 13:33:37 +0530 [thread overview]
Message-ID: <754242d35fd6a5d3fe39e7de96ca4e813d100acc.1784619898.git.naveen@kernel.org> (raw)
In-Reply-To: <cover.1784619898.git.naveen@kernel.org>
Switch to using apic_eilvt_count as the maximum EILVT register count.
Since this value is no longer a compile-time constant, update
eilvt_offsets to be dynamically allocated.
Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
arch/x86/include/asm/apicdef.h | 1 -
arch/x86/kernel/apic/apic.c | 7 +++++--
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index ba7657e75ad1..32a242ae0455 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -140,7 +140,6 @@
#define APIC_IER 0x480
#define APIC_EILVTn(n) (0x500 + 0x10 * n)
#define APIC_EILVT_NR_AMD_10H 4
-#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
#define APIC_BASE_MSR 0x800
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 83895ce954ef..2e98ab259ae0 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
* necessarily a BIOS bug.
*/
-static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
+static atomic_t *eilvt_offsets;
unsigned int apic_eilvt_count __ro_after_init;
static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
@@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
{
unsigned int rsvd, vector;
- if (offset >= APIC_EILVT_NR_MAX)
+ if (!eilvt_offsets || offset >= apic_eilvt_count)
return ~0;
rsvd = atomic_read(&eilvt_offsets[offset]);
@@ -418,6 +418,9 @@ static __init void init_eilvt(void)
if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
apic_eilvt_count = APIC_EILVT_NR_AMD_10H;
+
+ if (apic_eilvt_count)
+ eilvt_offsets = kzalloc_objs(atomic_t, apic_eilvt_count);
}
/*
--
2.54.0
prev parent reply other threads:[~2026-07-21 8:08 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-21 8:03 [PATCH v3 0/3] Support additional AMD EILVT registers Naveen N Rao (AMD)
2026-07-21 8:03 ` [PATCH v3 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Naveen N Rao (AMD)
2026-07-21 8:03 ` [PATCH v3 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Naveen N Rao (AMD)
2026-07-21 12:42 ` Thomas Gleixner
2026-07-22 14:04 ` Naveen N Rao
2026-07-21 8:03 ` Naveen N Rao (AMD) [this message]
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