From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
robh+dt@kernel.org, mathieu.poirier@linaro.org,
leo.yan@linaro.org, alexander.shishkin@linux.intel.com,
andy.gross@linaro.org, david.brown@linaro.org,
vivek.gautam@codeaurora.org, dianders@chromium.org,
sboyd@kernel.org, bjorn.andersson@linaro.org,
devicetree@vger.kernel.org, mark.rutland@arm.com
Cc: rnayak@codeaurora.org, sibis@codeaurora.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support
Date: Tue, 22 Jan 2019 20:32:51 +0530 [thread overview]
Message-ID: <75ed74af-6946-b86d-092e-42dc16e55308@codeaurora.org> (raw)
In-Reply-To: <1bd39862-0725-70ce-6535-fdb59569f683@arm.com>
Hi Suzuki,
Thanks for looking into this. Please find my response inline.
On 1/22/2019 7:30 PM, Suzuki K Poulose wrote:
> Hi Sai,
>
> On 01/22/2019 01:37 PM, Sai Prakash Ranjan wrote:
>> Add coresight components found on Qualcomm SDM845 SoC.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>>
>
> Sorry, but I hadn't noticed the PID override strings below. Please
> find the question.
>
[..]
>> + /*
>> + * On QCOM SDM845, we bypass the normal AMBA bus discovery
>> + * method by forcing the peripheral ID because of the wrong
>> + * value read from ETM PID registers.
>> + */
>
> What is the value read back from the ETM PIDx registers ? Do they
> provide inconsistent or incompatible value w.r.t the ETM/Coresight
> architecture ? If it is an unsupported CPU with proper values,
> you must add them to the table in etm4x driver.
>
The values read from ETM PIDx registers are actually inconsistent
and is different for some ETMs.
Below are the PIDs read for SDM845:
[ 5.996448] resname=etm@7040000 pid=001bb803
[ 6.052891] resname=etm@7140000 pid=001bb803
<snip> .. (Same pid=001bb803 for etm@7240000 to etm@7540000 but differs
for other 2 cpus as shown below)
[ 6.266687] resname=etm@7640000 pid=001bb802
[ 6.329171] resname=etm@7740000 pid=001bb802
This is the case for MSM8996 also as shown below where PID
value is not correct and has to be hardcoded.
For MSM8996:
resname=etm@3b40000 pid=102f0205
>> + etm@7040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + arm,primecell-periphid = <0x000bb95d> > + reg
>> = <0 0x07040000 0 0x1000>;
>> +
>> + cpu = <&CPU0>;
>> +
>
> You seem to be specifying the PID of A53 ETM all over, while at least
> one of your cores is ETMv4.2 (from the other patch) and A53 is not
> ETMv4.2. As above, it would be good to add the PID to the table.
>
As explained in above comment, PID values read are not correct. Please
let me know if I am not clear.
Thanks,
Sai
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2019-01-22 15:03 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-22 13:37 [PATCHv4 0/4] Add coresight support for SDM845 and MSM8996 Sai Prakash Ranjan
2019-01-22 13:37 ` [PATCHv4 1/4] arm64: dts: qcom: sdm845: Add Coresight support Sai Prakash Ranjan
2019-01-22 14:00 ` Suzuki K Poulose
2019-01-22 15:02 ` Sai Prakash Ranjan [this message]
2019-01-22 16:08 ` Suzuki K Poulose
2019-01-22 16:48 ` Sai Prakash Ranjan
2019-01-22 20:12 ` Suzuki K Poulose
2019-01-23 12:11 ` Sai Prakash Ranjan
2019-01-23 19:14 ` Mathieu Poirier
2019-01-23 20:17 ` Sai Prakash Ranjan
2019-01-24 16:07 ` Marc Gonzalez
2019-01-24 18:24 ` Sai Prakash Ranjan
2019-01-24 16:07 ` Mathieu Poirier
2019-01-24 18:31 ` Sai Prakash Ranjan
2019-01-24 11:19 ` Suzuki K Poulose
2019-01-24 18:21 ` Sai Prakash Ranjan
2019-01-28 17:15 ` Mathieu Poirier
2019-01-28 19:17 ` Sai Prakash Ranjan
2019-01-22 13:37 ` [PATCHv4 2/4] arm64: dts: qcom: msm8996: " Sai Prakash Ranjan
2019-01-22 13:37 ` [PATCHv4 3/4] coresight: etm4x: Add support to enable ETMv4.2 Sai Prakash Ranjan
2019-01-22 13:37 ` [PATCHv4 4/4] arm64: dts: qcom: sdm845: Remove the duplicate header inclusion Sai Prakash Ranjan
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