Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur

[Taniya Das <taniya.das@oss.qualcomm.com>]

On 7/30/2025 4:55 PM, Abel Vesa wrote:
> On 25-07-29 11:12:37, Taniya Das wrote:
>> Add a clock driver for the TCSR clock controller found on Glymur, which
>> provides refclks for PCIE, USB, and UFS.
>>
>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>> ---
>>  drivers/clk/qcom/Kconfig         |   8 ++
>>  drivers/clk/qcom/Makefile        |   1 +
>>  drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++
>>  3 files changed, 266 insertions(+)
>>
> 
> [...]
> 
>> +
>> +static struct clk_branch tcsr_edp_clkref_en = {
>> +	.halt_reg = 0x1c,
>> +	.halt_check = BRANCH_HALT_DELAY,
>> +	.clkr = {
>> +		.enable_reg = 0x1c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(const struct clk_init_data) {
>> +			.name = "tcsr_edp_clkref_en",
>> +			.ops = &clk_branch2_ops,
> 
> As discussed off-list, these clocks need to have the bi_tcxo as parent.
> 
> Otherwise, as far as the CCF is concerned these clocks will have rate 0,
> which is obviously not the case.
> 
> Bringing this here since there is a disconnect between X Elite and
> Glymur w.r.t this now.


The ref clocks are not required to be have a parent of bi_tcxo as these
ideally can be left enabled(as a subsystem requirement) even if HLOS
(APSS) goes to suspend. With the bi_tcxo parent the ARC vote from
HLOS/APSS will not allow APSS to collapse.

If any consumers needs the clock rate, the driver should take the
BI_TCXO handle.


-- 
Thanks,
Taniya Das