mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: <Parthiban.Veerasooran@microchip.com>
To: <andrew@lunn.ch>
Cc: <davem@davemloft.net>, <edumazet@google.com>, <kuba@kernel.org>,
	<pabeni@redhat.com>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
	<corbet@lwn.net>, <Steen.Hegelund@microchip.com>,
	<rdunlap@infradead.org>, <horms@kernel.org>,
	<casper.casan@gmail.com>, <netdev@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-doc@vger.kernel.org>, <Horatiu.Vultur@microchip.com>,
	<Woojung.Huh@microchip.com>, <Nicolas.Ferre@microchip.com>,
	<UNGLinuxDriver@microchip.com>,
	<Thorsten.Kummermehr@microchip.com>
Subject: Re: [PATCH net-next v2 5/9] net: ethernet: oa_tc6: implement internal PHY initialization
Date: Tue, 31 Oct 2023 04:20:48 +0000	[thread overview]
Message-ID: <7873124e-d7b2-4983-9be3-f85865d46de2@microchip.com> (raw)
In-Reply-To: <5c240b3b-60c2-45bb-8861-e3a8de28d00f@lunn.ch>

Hi Andrew,

On 24/10/23 6:26 am, Andrew Lunn wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
>> +     /* Minimum supported Chunk Payload Size */
>>        mincps = FIELD_GET(MINCPS, regval);
>> +     /* Cut-Through Capability */
>>        ctc = (regval & CTC) ? true : false;
> 
> These comment should be in the patch which added these, not here.
Ah yes. Will correct it.
> 
>> +     /* Direct PHY Register Access Capability */
>> +     dprac = (regval & DPRAC) ? true : false;
>> +     /* Indirect PHY Register access Capability */
>> +     iprac = (regval & IPRAC) ? true : false;
>>
>>        regval = 0;
>>        oa_node = of_get_child_by_name(spi->dev.of_node, "oa-tc6");
>> @@ -242,7 +257,7 @@ static int oa_tc6_configure(struct oa_tc6 *tc6)
>>                        if (tc6->cps < mincps)
>>                                return -ENODEV;
>>                } else {
>> -                     tc6->cps = 64;
>> +                     tc6->cps = OA_TC6_MAX_CPS;
> 
> This also should of been in an earlier patch.
Yes, will correct it.
> 
>>                }
>>                if (of_property_present(oa_node, "oa-txcte")) {
>>                        /* Return error if the tx cut through mode is configured
>> @@ -266,8 +281,26 @@ static int oa_tc6_configure(struct oa_tc6 *tc6)
>>                        regval |= PROTE;
>>                        tc6->prote = true;
>>                }
>> +             if (of_property_present(oa_node, "oa-dprac")) {
>> +                     /* Return error if the direct phy register access mode
>> +                      * is configured but it is not supported by MAC-PHY.
>> +                      */
>> +                     if (dprac)
>> +                             tc6->dprac = true;
>> +                     else
>> +                             return -ENODEV;
>> +             }
> 
> This is not in the binding. Why do we even need to be able to
> configure it. Direct is faster, so use it is available. If not, use
> indirect. And if both dprac and iproc are false, dev_err() and
> -ENODEV.
Ok, I will remove this option even in the next patch and will go with 
the option read from the capability register (STDCAP).
> 
>> +static int oa_tc6_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
> 
> It would be good to put direct in the name. If somebody implements
> indirect, it will make the naming easier.
Yes sure.
> 
>> +{
>> +     struct oa_tc6 *tc6 = bus->priv;
>> +     u32 regval;
>> +     bool ret;
>> +
>> +     ret = oa_tc6_read_register(tc6, 0xFF00 | (idx & 0xFF), &regval);
>> +     if (ret)
>> +             return -ENODEV;
>> +
>> +     return regval;
>> +}
>> +
>> +static int oa_tc6_mdiobus_write(struct mii_bus *bus, int phy_id, int idx,
>> +                             u16 val)
>> +{
>> +     struct oa_tc6 *tc6 = bus->priv;
>> +
>> +     return oa_tc6_write_register(tc6, 0xFF00 | (idx & 0xFF), val);
>> +}
>> +
>> +static int oa_tc6_phy_init(struct oa_tc6 *tc6)
>> +{
>> +     int ret;
>> +
>> +     if (tc6->dprac) {
> 
> You can avoid the indentation by first checking indirect is the only
> choice, and doing a dev_err() followed by return -ENODEV.
Ah ok, will do it.
> 
>> +             tc6->mdiobus = mdiobus_alloc();
>> +             if (!tc6->mdiobus) {
>> +                     netdev_err(tc6->netdev, "MDIO bus alloc failed\n");
>> +                     return -ENODEV;
>> +             }
>> +
>> +             tc6->mdiobus->phy_mask = ~(u32)BIT(1);
> 
> Does the standard define this ? BIT(1), not BIT(0)?
Ok, I think here is a typo. Will correct it.
> 
>>   /**
>>    * oa_tc6_init - allocates and intializes oa_tc6 structure.
>>    * @spi: device with which data will be exchanged.
>> - * @prote: control data (register) read/write protection enable/disable.
> 
> Something else which should of been in the previous patch. Please look
> through this patch and find all the other instances.
Yes sure. Will correct it.
> 
>> + * @netdev: network device to use.
>>    *
>>    * Returns pointer reference to the oa_tc6 structure if all the memory
>>    * allocation success otherwise NULL.
>>    */
>> -struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
>> +struct oa_tc6 *oa_tc6_init(struct spi_device *spi, struct net_device *netdev)
>>   {
>>        struct oa_tc6 *tc6;
>>
>> @@ -395,15 +521,19 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
>>        if (!tc6)
>>                return NULL;
>>
>> +     /* Allocate memory for the control tx buffer used for SPI transfer. */
>>        tc6->ctrl_tx_buf = devm_kzalloc(&spi->dev, TC6_CTRL_BUF_SIZE, GFP_KERNEL);
>>        if (!tc6->ctrl_tx_buf)
>>                return NULL;
>>
>> +     /* Allocate memory for the control rx buffer used for SPI transfer. */
>>        tc6->ctrl_rx_buf = devm_kzalloc(&spi->dev, TC6_CTRL_BUF_SIZE, GFP_KERNEL);
>>        if (!tc6->ctrl_rx_buf)
>>                return NULL;
>>
>>        tc6->spi = spi;
>> +     tc6->netdev = netdev;
>> +     SET_NETDEV_DEV(netdev, &spi->dev);
>>
>>        /* Perform MAC-PHY software reset */
>>        if (oa_tc6_sw_reset(tc6)) {
>> @@ -417,10 +547,27 @@ struct oa_tc6 *oa_tc6_init(struct spi_device *spi)
>>                return NULL;
>>        }
>>
>> +     /* Initialize PHY */
>> +     if (oa_tc6_phy_init(tc6)) {
>> +             dev_err(&spi->dev, "PHY initialization failed\n");
>> +             return NULL;
>> +     }
>> +
>>        return tc6;
>>   }
>>   EXPORT_SYMBOL_GPL(oa_tc6_init);
>>
>> +/**
>> + * oa_tc6_exit - exit function.
>> + * @tc6: oa_tc6 struct.
>> + *
>> + */
>> +void oa_tc6_exit(struct oa_tc6 *tc6)
>> +{
>> +     oa_tc6_phy_exit(tc6);
>> +}
>> +EXPORT_SYMBOL_GPL(oa_tc6_exit);
>> +
>>   MODULE_DESCRIPTION("OPEN Alliance 10BASE‑T1x MAC‑PHY Serial Interface Lib");
>>   MODULE_AUTHOR("Parthiban Veerasooran <parthiban.veerasooran@microchip.com>");
>>   MODULE_LICENSE("GPL");
>> diff --git a/include/linux/oa_tc6.h b/include/linux/oa_tc6.h
>> index 378636fd9ca8..36b729c384ac 100644
>> --- a/include/linux/oa_tc6.h
>> +++ b/include/linux/oa_tc6.h
>> @@ -5,54 +5,59 @@
>>    * Author: Parthiban Veerasooran <parthiban.veerasooran@microchip.com>
>>    */
>>
>> +#include <linux/etherdevice.h>
>>   #include <linux/spi/spi.h>
>>
>>   /* Control header */
>> -#define CTRL_HDR_DNC         BIT(31)         /* Data-Not-Control */
>> -#define CTRL_HDR_HDRB                BIT(30)         /* Received Header Bad */
>> -#define CTRL_HDR_WNR         BIT(29)         /* Write-Not-Read */
>> -#define CTRL_HDR_AID         BIT(28)         /* Address Increment Disable */
>> -#define CTRL_HDR_MMS         GENMASK(27, 24) /* Memory Map Selector */
>> -#define CTRL_HDR_ADDR                GENMASK(23, 8)  /* Address */
>> -#define CTRL_HDR_LEN         GENMASK(7, 1)   /* Length */
>> -#define CTRL_HDR_P           BIT(0)          /* Parity Bit */
>> +#define CTRL_HDR_DNC BIT(31)         /* Data-Not-Control */
>> +#define CTRL_HDR_HDRB        BIT(30)         /* Received Header Bad */
>> +#define CTRL_HDR_WNR BIT(29)         /* Write-Not-Read */
>> +#define CTRL_HDR_AID BIT(28)         /* Address Increment Disable */
>> +#define CTRL_HDR_MMS GENMASK(27, 24) /* Memory Map Selector */
>> +#define CTRL_HDR_ADDR        GENMASK(23, 8)  /* Address */
>> +#define CTRL_HDR_LEN GENMASK(7, 1)   /* Length */
>> +#define CTRL_HDR_P   BIT(0)          /* Parity Bit */
> 
> Please don't change the whitespace like this.
Ah yes, will correct it.

Best Regards,
Parthiban V
> 
>         Andrew


  reply	other threads:[~2023-10-31  4:21 UTC|newest]

Thread overview: 63+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-23 15:46 [PATCH net-next v2 0/9] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Parthiban Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 1/9] net: ethernet: implement OPEN Alliance control transaction interface Parthiban Veerasooran
2023-10-23 21:28   ` Andrew Lunn
2023-10-25 11:16     ` Parthiban.Veerasooran
2023-10-26 19:46       ` Andrew Lunn
2023-10-27  7:15         ` Parthiban.Veerasooran
2023-10-23 23:09   ` kernel test robot
2023-10-25 19:09   ` kernel test robot
2023-10-23 15:46 ` [PATCH net-next v2 2/9] net: ethernet: oa_tc6: implement mac-phy software reset Parthiban Veerasooran
2023-10-23 22:43   ` Andrew Lunn
2023-10-25 11:39     ` Parthiban.Veerasooran
2023-10-26 20:01       ` Andrew Lunn
2023-10-27  7:00         ` Parthiban.Veerasooran
2023-10-25 11:39     ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 3/9] net: ethernet: oa_tc6: implement OA TC6 configuration function Parthiban Veerasooran
2023-10-23 22:58   ` Andrew Lunn
2023-10-25 12:02     ` Parthiban.Veerasooran
2023-10-26 20:06       ` Andrew Lunn
2023-10-27  7:10         ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 4/9] dt-bindings: net: add OPEN Alliance 10BASE-T1x MAC-PHY Serial Interface Parthiban Veerasooran
2023-10-23 17:40   ` Rob Herring
2023-10-25 12:28     ` Parthiban.Veerasooran
2023-10-24  0:37   ` Andrew Lunn
2023-10-27  9:12     ` Parthiban.Veerasooran
     [not found]       ` <d6377de8-603f-4ac1-a691-b79c46a5057b@lunn.ch>
2023-10-30 10:09         ` Parthiban.Veerasooran
2023-10-24  7:44   ` Krzysztof Kozlowski
2023-10-31 12:59     ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 5/9] net: ethernet: oa_tc6: implement internal PHY initialization Parthiban Veerasooran
2023-10-24  0:56   ` Andrew Lunn
2023-10-31  4:20     ` Parthiban.Veerasooran [this message]
2023-10-31 12:48       ` Andrew Lunn
2023-11-01  4:53         ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 6/9] dt-bindings: net: oa-tc6: add PHY register access capability Parthiban Veerasooran
2023-10-24  1:21   ` Andrew Lunn
2023-10-31  4:22     ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 7/9] net: ethernet: oa_tc6: implement data transaction interface Parthiban Veerasooran
2023-10-24  2:07   ` Andrew Lunn
2023-10-31  8:26     ` Parthiban.Veerasooran
2023-10-23 15:46 ` [PATCH net-next v2 8/9] microchip: lan865x: add driver support for Microchip's LAN865X MACPHY Parthiban Veerasooran
2023-10-24  2:33   ` Andrew Lunn
2023-10-31 11:04     ` Parthiban.Veerasooran
2023-10-31 12:53       ` Andrew Lunn
2023-11-01  4:51         ` Parthiban.Veerasooran
2023-10-24 11:57   ` Krzysztof Kozlowski
2023-10-31 10:25     ` Parthiban.Veerasooran
2023-11-02 12:20   ` Ramón Nordin Rodriguez
2023-11-02 12:39     ` Andrew Lunn
2023-11-02 13:40       ` Ramón Nordin Rodriguez
2023-11-03 14:59     ` Parthiban.Veerasooran
2023-11-06  8:59       ` Ramón Nordin Rodriguez
2023-10-23 15:46 ` [PATCH net-next v2 9/9] dt-bindings: net: add Microchip's LAN865X 10BASE-T1S MACPHY Parthiban Veerasooran
2023-10-23 17:40   ` Rob Herring
2023-10-30 12:41     ` Parthiban.Veerasooran
2023-10-24  8:03   ` Krzysztof Kozlowski
2023-10-30 13:16     ` Parthiban.Veerasooran
2023-10-30 14:45       ` Krzysztof Kozlowski
2023-11-02 13:31         ` Parthiban.Veerasooran
2024-03-24 11:55 ` [PATCH net-next v2 0/9] Add support for OPEN Alliance 10BASE-T1x MACPHY Serial Interface Benjamin Bigler
2024-03-25 13:24   ` Parthiban.Veerasooran
2024-03-25 14:01     ` Andrew Lunn
2024-03-26  9:43       ` Parthiban.Veerasooran
2024-04-03 21:40     ` Benjamin Bigler
2024-04-08 13:41       ` Parthiban.Veerasooran

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=7873124e-d7b2-4983-9be3-f85865d46de2@microchip.com \
    --to=parthiban.veerasooran@microchip.com \
    --cc=Horatiu.Vultur@microchip.com \
    --cc=Nicolas.Ferre@microchip.com \
    --cc=Steen.Hegelund@microchip.com \
    --cc=Thorsten.Kummermehr@microchip.com \
    --cc=UNGLinuxDriver@microchip.com \
    --cc=Woojung.Huh@microchip.com \
    --cc=andrew@lunn.ch \
    --cc=casper.casan@gmail.com \
    --cc=conor+dt@kernel.org \
    --cc=corbet@lwn.net \
    --cc=davem@davemloft.net \
    --cc=devicetree@vger.kernel.org \
    --cc=edumazet@google.com \
    --cc=horms@kernel.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=kuba@kernel.org \
    --cc=linux-doc@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=netdev@vger.kernel.org \
    --cc=pabeni@redhat.com \
    --cc=rdunlap@infradead.org \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®