[PATCH 0/2] phy: Add the Siflower SF19A2890 USB 2.0 PHY

[PATCH 0/2] phy: Add the Siflower SF19A2890 USB 2.0 PHY

[Joseph Telaak via B4 Relay]

This series adds a binding and a driver for the USB 2.0 PHY of the
Siflower SF19A2890, a MIPS SoC for home routers. The PHY takes its
reference clock and its two resets from the USB block's clock and reset
manager, which goes to the clk tree.

The driver is Chuanhong Guo's, from his SF19A2890 branch [1], with my
changes noted.

The SoC support itself (MACH_SIFLOWER_MIPS) goes through the MIPS tree;
until then the driver builds with COMPILE_TEST. The DWC2 part goes to
the USB tree.

The MAINTAINERS entry that covers these files comes with the MIPS series
"MIPS: Add support for the Siflower SF19A2890"; this series applies on
its own. That entry is also why checkpatch's question about updating
MAINTAINERS for the new files is left unanswered here.

Tested on a GL.iNet GL-SFT1200 with the DWC2 patches: a USB stick
enumerates at 480 Mb/s and reads at 5.6 MB/s (5.0 MB/s with the same
stick on OpenWrt's 6.18 kernel), and comes back after unplugging and
replugging it twice.

[1] https://github.com/981213/linux/commits/siflower-7.1

---
Chuanhong Guo (1):
      phy: siflower: Add SF19A2890 USB 2.0 PHY driver

Joseph Telaak (1):
      dt-bindings: phy: Add Siflower SF19A2890 USB 2.0 PHY

 .../bindings/phy/siflower,sf19a2890-usb-phy.yaml   |  58 +++++++++
 drivers/phy/Kconfig                                |   1 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/siflower/Kconfig                       |  12 ++
 drivers/phy/siflower/Makefile                      |   2 +
 drivers/phy/siflower/phy-sf19a2890-usb.c           | 143 +++++++++++++++++++++
 6 files changed, 217 insertions(+)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261102-sf19a2890-usb-phy-5bb644992750

Best regards,
--  
Joseph Telaak <joseph@telaak.dev>

[PATCH 1/2] dt-bindings: phy: Add Siflower SF19A2890 USB 2.0 PHY

[Joseph Telaak via B4 Relay]

From: Joseph Telaak <joseph@telaak.dev>

The USB 2.0 PHY of the Siflower SF19A2890 serves its DWC2 controller.
It takes a reference clock and two resets, power-on and PHY, from the
USB block's clock and reset manager.

Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
 .../bindings/phy/siflower,sf19a2890-usb-phy.yaml   | 58 ++++++++++++++++++++++
 1 file changed, 58 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml b/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml
new file mode 100644
index 000000000..77b8e35d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/siflower,sf19a2890-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Siflower SF19A2890 USB 2.0 PHY
+
+maintainers:
+  - Joseph Telaak <joseph@telaak.dev>
+
+description:
+  The USB 2.0 PHY of the Siflower SF19A2890, used by its DWC2 controller.
+
+properties:
+  compatible:
+    const: siflower,sf19a2890-usb-phy
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+    description: PHY reference clock
+
+  resets:
+    items:
+      - description: power-on reset
+      - description: PHY reset
+
+  reset-names:
+    items:
+      - const: por
+      - const: phy
+
+  "#phy-cells":
+    const: 0
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - resets
+  - reset-names
+  - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    usb-phy@19e0c040 {
+        compatible = "siflower,sf19a2890-usb-phy";
+        reg = <0x19e0c040 0x60>;
+        clocks = <&usb_crm 2>;
+        resets = <&usb_crm 1>, <&usb_crm 2>;
+        reset-names = "por", "phy";
+        #phy-cells = <0>;
+    };

-- 
Git-155)

[PATCH 2/2] phy: siflower: Add SF19A2890 USB 2.0 PHY driver

[Joseph Telaak via B4 Relay]

From: Chuanhong Guo <gch981213@gmail.com>

Add a driver for the USB 2.0 PHY of the Siflower SF19A2890. Powering it
on enables its reference clock, releases its two resets and takes it
out of sleep.

Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
[jt: from Chuanhong's siflower-7.1 branch, the SF19A2890 PHY only; reset
 names "por" and "phy", dev_err_probe() for the resets, drop the unused
 includes and drvdata, Kconfig dependencies and help, commit message,
 subject]
Signed-off-by: Joseph Telaak <joseph@telaak.dev>
---
 drivers/phy/Kconfig                      |   1 +
 drivers/phy/Makefile                     |   1 +
 drivers/phy/siflower/Kconfig             |  12 +++
 drivers/phy/siflower/Makefile            |   2 +
 drivers/phy/siflower/phy-sf19a2890-usb.c | 143 +++++++++++++++++++++++++++++++
 5 files changed, 159 insertions(+)

diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 105fbe408..8ba351e23 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -194,6 +194,7 @@ source "drivers/phy/realtek/Kconfig"
 source "drivers/phy/renesas/Kconfig"
 source "drivers/phy/rockchip/Kconfig"
 source "drivers/phy/samsung/Kconfig"
+source "drivers/phy/siflower/Kconfig"
 source "drivers/phy/socionext/Kconfig"
 source "drivers/phy/sophgo/Kconfig"
 source "drivers/phy/spacemit/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index c6dd02003..8c917c4c5 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_GENERIC_PHY)		+= allwinner/	\
 					   renesas/	\
 					   rockchip/	\
 					   samsung/	\
+					   siflower/	\
 					   socionext/	\
 					   sophgo/	\
 					   spacemit/	\
diff --git a/drivers/phy/siflower/Kconfig b/drivers/phy/siflower/Kconfig
new file mode 100644
index 000000000..5ae1f83d1
--- /dev/null
+++ b/drivers/phy/siflower/Kconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config PHY_SF19A2890_USB
+	tristate "Siflower SF19A2890 USB 2.0 PHY driver"
+	depends on MACH_SIFLOWER_MIPS || COMPILE_TEST
+	depends on OF
+	select GENERIC_PHY
+	help
+	  Enable this to support the USB 2.0 PHY of the Siflower SF19A2890,
+	  used by its DWC2 controller. Its reference clock and its resets
+	  come from the USB block's clock and reset manager.
+	  Say M or Y if the kernel is to run on this SoC.
diff --git a/drivers/phy/siflower/Makefile b/drivers/phy/siflower/Makefile
new file mode 100644
index 000000000..a12383193
--- /dev/null
+++ b/drivers/phy/siflower/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_PHY_SF19A2890_USB)	+= phy-sf19a2890-usb.o
diff --git a/drivers/phy/siflower/phy-sf19a2890-usb.c b/drivers/phy/siflower/phy-sf19a2890-usb.c
new file mode 100644
index 000000000..115e38b8c
--- /dev/null
+++ b/drivers/phy/siflower/phy-sf19a2890-usb.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy/phy.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#define USB_SLEEPM 0x4
+
+struct sf19a2890_usb_phy {
+	struct device *dev;
+	struct clk *phy_clk;
+	struct reset_control *usb_phy_rst;
+	struct reset_control *power_on_rst;
+	void __iomem *base;
+};
+
+static int sf19a2890_usb_phy_power_on(struct phy *phy)
+{
+	struct sf19a2890_usb_phy *p_phy = phy_get_drvdata(phy);
+	int ret;
+
+	ret = clk_prepare_enable(p_phy->phy_clk);
+	if (ret < 0) {
+		dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
+		return ret;
+	}
+
+	ret = reset_control_deassert(p_phy->usb_phy_rst);
+	if (ret)
+		goto err1;
+
+	ret = reset_control_deassert(p_phy->power_on_rst);
+	if (ret)
+		goto err2;
+
+	writel(1, p_phy->base + USB_SLEEPM);
+	return 0;
+err2:
+	reset_control_assert(p_phy->usb_phy_rst);
+err1:
+	clk_disable_unprepare(p_phy->phy_clk);
+	return ret;
+}
+
+static int sf19a2890_usb_phy_power_off(struct phy *phy)
+{
+	struct sf19a2890_usb_phy *p_phy = phy_get_drvdata(phy);
+
+	writel(0, p_phy->base + USB_SLEEPM);
+	reset_control_assert(p_phy->power_on_rst);
+	reset_control_assert(p_phy->usb_phy_rst);
+	clk_disable_unprepare(p_phy->phy_clk);
+	return 0;
+}
+
+static const struct phy_ops sf19a2890_usb_phy_ops = {
+	.power_on = sf19a2890_usb_phy_power_on,
+	.power_off = sf19a2890_usb_phy_power_off,
+	.owner = THIS_MODULE,
+};
+
+static int sf19a2890_usb_phy_probe(struct platform_device *pdev)
+{
+	struct sf19a2890_usb_phy *p_phy;
+	struct phy_provider *provider;
+	struct phy *phy;
+	int ret;
+
+	p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
+	if (!p_phy)
+		return -ENOMEM;
+
+	p_phy->dev = &pdev->dev;
+
+	p_phy->base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(p_phy->base))
+		return PTR_ERR(p_phy->base);
+
+	p_phy->phy_clk = devm_clk_get(p_phy->dev, NULL);
+	if (IS_ERR(p_phy->phy_clk))
+		return dev_err_probe(p_phy->dev, PTR_ERR(p_phy->phy_clk),
+				     "failed to get usb phy clock\n");
+
+	p_phy->power_on_rst =
+		devm_reset_control_get_exclusive(&pdev->dev, "por");
+	if (IS_ERR(p_phy->power_on_rst))
+		return dev_err_probe(p_phy->dev, PTR_ERR(p_phy->power_on_rst),
+				     "failed to get power-on reset\n");
+
+	ret = reset_control_assert(p_phy->power_on_rst);
+	if (ret)
+		return ret;
+
+	p_phy->usb_phy_rst =
+		devm_reset_control_get_exclusive(&pdev->dev, "phy");
+	if (IS_ERR(p_phy->usb_phy_rst))
+		return dev_err_probe(p_phy->dev, PTR_ERR(p_phy->usb_phy_rst),
+				     "failed to get PHY reset\n");
+
+	ret = reset_control_assert(p_phy->usb_phy_rst);
+	if (ret)
+		return ret;
+
+	phy = devm_phy_create(p_phy->dev, NULL, &sf19a2890_usb_phy_ops);
+	if (IS_ERR(phy))
+		return dev_err_probe(p_phy->dev, PTR_ERR(phy),
+				     "Failed to create PHY\n");
+
+	phy_set_drvdata(phy, p_phy);
+
+	provider =
+		devm_of_phy_provider_register(p_phy->dev, of_phy_simple_xlate);
+	if (IS_ERR(provider))
+		return dev_err_probe(p_phy->dev, PTR_ERR(provider),
+				     "Failed to register PHY provider\n");
+
+	return 0;
+}
+
+static const struct of_device_id sf19a2890_usb_phy_of_match[] = {
+	{
+		.compatible = "siflower,sf19a2890-usb-phy",
+	},
+	{ }
+};
+MODULE_DEVICE_TABLE(of, sf19a2890_usb_phy_of_match);
+
+static struct platform_driver sf19a2890_usb_phy_driver = {
+	.probe		= sf19a2890_usb_phy_probe,
+	.driver		= {
+		.name	= "sf19a2890-usb-phy",
+		.of_match_table = sf19a2890_usb_phy_of_match,
+	},
+};
+module_platform_driver(sf19a2890_usb_phy_driver);
+
+MODULE_AUTHOR("Ziying Wu <ziying.wu@siflower.com.cn>");
+MODULE_DESCRIPTION("Siflower SF19A2890 USB2.0 PHY driver");
+MODULE_LICENSE("GPL");

-- 
Git-155)

Re: [PATCH 1/2] dt-bindings: phy: Add Siflower SF19A2890 USB 2.0 PHY

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 2273 bytes --]

On Wed, Nov 04, 2026 at 02:21:52AM -0500, Joseph Telaak via B4 Relay wrote:
> From: Joseph Telaak <joseph@telaak.dev>
> 
> The USB 2.0 PHY of the Siflower SF19A2890 serves its DWC2 controller.
> It takes a reference clock and two resets, power-on and PHY, from the
> USB block's clock and reset manager.
> 
> Signed-off-by: Joseph Telaak <joseph@telaak.dev>
> ---
>  .../bindings/phy/siflower,sf19a2890-usb-phy.yaml   | 58 ++++++++++++++++++++++
>  1 file changed, 58 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml b/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml
> new file mode 100644
> index 000000000..77b8e35d8
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/siflower,sf19a2890-usb-phy.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/siflower,sf19a2890-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Siflower SF19A2890 USB 2.0 PHY
> +
> +maintainers:
> +  - Joseph Telaak <joseph@telaak.dev>
> +
> +description:
> +  The USB 2.0 PHY of the Siflower SF19A2890, used by its DWC2 controller.
> +
> +properties:
> +  compatible:
> +    const: siflower,sf19a2890-usb-phy
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +    description: PHY reference clock
> +
> +  resets:
> +    items:
> +      - description: power-on reset
> +      - description: PHY reset
> +
> +  reset-names:
> +    items:
> +      - const: por
> +      - const: phy
> +
> +  "#phy-cells":
> +    const: 0
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - resets
> +  - reset-names
> +  - "#phy-cells"
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    usb-phy@19e0c040 {
> +        compatible = "siflower,sf19a2890-usb-phy";
> +        reg = <0x19e0c040 0x60>;

That's a weird offset and size.
What lies in the regions around this device?

> +        clocks = <&usb_crm 2>;
> +        resets = <&usb_crm 1>, <&usb_crm 2>;
> +        reset-names = "por", "phy";
> +        #phy-cells = <0>;
> +    };
> 
> -- 
> Git-155)
> 
> 

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Re: [PATCH 1/2] dt-bindings: phy: Add Siflower SF19A2890 USB 2.0 PHY

[Joseph Telaak]

> > +        reg = <0x19e0c040 0x60>;
>
> That's a weird offset and size.
> What lies in the regions around this device?

It sits in the 1 KiB from 0x19e0c000 up to the next block at
0x19e0c400. At 0x0, 0x4 and 0xc are the reset, clock gate and bus output
enable registers of the USB clock and reset manager, which the clk
series describes as siflower,sf19a2890-usb-crm; 0x8 holds a value I
have no documentation for. The OpenWrt port gives the PHY 0x40-0x9f,
and its driver only uses 0x44, the PHY's sleep control. Read from
U-Boot, registers between 0x40 and 0x8f hold non-zero values I have no
documentation for either, and the rest reads as 0. The GMAC's
configuration registers sit the same way, at 0x40 past its clock and
reset manager at 0x19e04400.

If you'd prefer one node for the whole region, providing the clocks,
resets and the PHY, I'll restructure it that way for v2.

Re: [PATCH 2/2] phy: siflower: Add SF19A2890 USB 2.0 PHY driver

[Philipp Zabel]

On Mi, 2026-11-04 at 02:21 -0500, Joseph Telaak via B4 Relay wrote:
> From: Chuanhong Guo <gch981213@gmail.com>
> 
> Add a driver for the USB 2.0 PHY of the Siflower SF19A2890. Powering it
> on enables its reference clock, releases its two resets and takes it
> out of sleep.
> 
> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
> [jt: from Chuanhong's siflower-7.1 branch, the SF19A2890 PHY only; reset
>  names "por" and "phy", dev_err_probe() for the resets, drop the unused
>  includes and drvdata, Kconfig dependencies and help, commit message,
>  subject]
> Signed-off-by: Joseph Telaak <joseph@telaak.dev>
> ---
>  drivers/phy/Kconfig                      |   1 +
>  drivers/phy/Makefile                     |   1 +
>  drivers/phy/siflower/Kconfig             |  12 +++
>  drivers/phy/siflower/Makefile            |   2 +
>  drivers/phy/siflower/phy-sf19a2890-usb.c | 143 +++++++++++++++++++++++++++++++
>  5 files changed, 159 insertions(+)
> 
[...]
> --- /dev/null
> +++ b/drivers/phy/siflower/phy-sf19a2890-usb.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0
> +
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/reset.h>
> +
> +#define USB_SLEEPM 0x4
> +
> +struct sf19a2890_usb_phy {
> +	struct device *dev;
> +	struct clk *phy_clk;
> +	struct reset_control *usb_phy_rst;
> +	struct reset_control *power_on_rst;

Since these two resets are always toggled together, consider using the
reset_control_bulk API for both.

regards
Philipp