Re: [PATCH] soc: mediatek: mmsys: Add sw0_rst_offset for MT8192

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

On Tue, 2022-03-22 at 10:20 +0100, AngeloGioacchino Del Regno wrote:
> MT8192 has the same sw0 reset offset as MT8183: add the parameter
> to be able to use mmsys as a reset controller for managing at
> least the DSI reset line.
> 
> Signed-off-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> ---
>  drivers/soc/mediatek/mtk-mmsys.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 4fc4c2c9ea20..f69521fabcce 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -70,6 +70,7 @@ static const struct mtk_mmsys_driver_data
> mt8192_mmsys_driver_data = {
>  	.clk_driver = "clk-mt8192-mm",
>  	.routes = mmsys_mt8192_routing_table,
>  	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
> +	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
>  };
>  
>  static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data =
> {

Hello Angelo,

Thanks for your patch.
But from register map for mmsys, the offset is 0x160 and DSI reset bit
is 15.

datasheet: MT8192 Tablet Application Processor Software Register
Table/4.1 Display Controller.pdf

BRs,
Rex