Re: [PATCH RFC v2 5/6] x86: Use global pages when PTI is disabled

[Nadav Amit <nadav.amit@gmail.com>]

Dave Hansen <dave.hansen@linux.intel.com> wrote:

> On 02/15/2018 11:53 AM, Andy Lutomirski wrote:
>>> --- a/arch/x86/include/asm/tlbflush.h
>>> +++ b/arch/x86/include/asm/tlbflush.h
>>> @@ -319,6 +319,12 @@ static inline void set_cpu_pti_disable(unsigned short disable)
>>>        WARN_ON_ONCE(preemptible());
>>> 
>>>        pti_update_user_cs64(cpu_pti_disable(), disable);
>>> +       if (__supported_pte_mask & _PAGE_GLOBAL) {
>>> +               if (disable)
>>> +                       cr4_set_bits(X86_CR4_PGE);
>>> +               else
>>> +                       cr4_clear_bits(X86_CR4_PGE);
>>> +       }
>> This will be *extremely* slow, and I don't see the point at all.  What
>> are you accomplishing here?
> 
> It won't be slow if you always run compat processes, I guess.
> 
> But mixing these in here will eat a big chunk of the benefit of having
> global pages (or PCIDs for that matter) in the first place.

These are all good points. The idea was to allow workloads like Apache, that
spawn multiple processes that frequently perform context-switches to incur
TLB misses on kernel pages. 

The double-flushing was not intentional - I missed it. Anyhow, based on your
comments, and because I don’t see an easy way to make the global
cpu_entry_area (your recent patches) to work with this patch, I think I will
drop this patch.