* [PATCH v6 0/3] Add CRU support for rk3576 SoC
@ 2024-08-22 19:49 Detlev Casanova
2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova
` (2 more replies)
0 siblings, 3 replies; 8+ messages in thread
From: Detlev Casanova @ 2024-08-22 19:49 UTC (permalink / raw)
To: linux-kernel
Cc: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel,
Elaine Zhang, Detlev Casanova, linux-clk, devicetree,
linux-arm-kernel, linux-rockchip, kernel
Add support for clocks and resets on the rk3576.
Patches from downstream have been squashed and rebased.
The resets have been renumbered without gaps and their actual register/bit
information is set in rst-rk3576.c as it has been done for rk3588.
Also add the pll_rk3588_ddr pll type that is used by the ppll clock.
Changes since v5:
- Use mandatory syscon lookup instead of optional grf phandle
- Add pll_rk3588_ddr type to always have correct rate values
Changes since v4:
- Fix commit message with idx starting at 0
- Stash all bindings commits
- Cleanup example and add me as maintainer
Changes since v3:
- Add missing include in bindings
Changes since v2:
- Renumber IDs from 0
- Commit clock header with clock bindings
- Add missing resets on sub-cores
- Add redundant fields in bindings
Changes since v1:
- Remove reset defines that are probably out of the main core
- Separate resets and clocks bindings
- Renumber the resets without gaps
Detlev.
Detlev Casanova (1):
dt-bindings: clock, reset: Add support for rk3576
Elaine Zhang (2):
clk: rockchip: Add new pll type pll_rk3588_ddr
clk: rockchip: Add clock controller for the RK3576
.../bindings/clock/rockchip,rk3576-cru.yaml | 56 +
drivers/clk/rockchip/Kconfig | 7 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-pll.c | 6 +-
drivers/clk/rockchip/clk-rk3576.c | 1829 +++++++++++++++++
drivers/clk/rockchip/clk.h | 54 +
drivers/clk/rockchip/rst-rk3576.c | 652 ++++++
.../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++
.../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++
9 files changed, 3760 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml
create mode 100644 drivers/clk/rockchip/clk-rk3576.c
create mode 100644 drivers/clk/rockchip/rst-rk3576.c
create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h
create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h
--
2.46.0
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 2024-08-22 19:49 [PATCH v6 0/3] Add CRU support for rk3576 SoC Detlev Casanova @ 2024-08-22 19:49 ` Detlev Casanova 2024-08-26 11:04 ` Andy Yan 2024-08-26 14:00 ` [PATCH " Rob Herring (Arm) 2024-08-22 19:49 ` [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr Detlev Casanova 2024-08-22 19:49 ` [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 Detlev Casanova 2 siblings, 2 replies; 8+ messages in thread From: Detlev Casanova @ 2024-08-22 19:49 UTC (permalink / raw) To: linux-kernel Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, Detlev Casanova, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel, Sugar Zhang Add clock and reset ID defines for rk3576. Compared to the downstream bindings written by Elaine, this uses continous gapless IDs starting at 0. Thus all numbers are different between downstream and upstream, but names are kept exactly the same. Also add documentation for the rk3576 CRU core. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> --- .../bindings/clock/rockchip,rk3576-cru.yaml | 56 ++ .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++ .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++ 3 files changed, 1212 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml new file mode 100644 index 000000000000..9c9b36049c71 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip rk3576 Family Clock and Reset Control Module + +maintainers: + - Elaine Zhang <zhangqing@rock-chips.com> + - Heiko Stuebner <heiko@sntech.de> + - Detlev Casanova <detlev.casanova@collabora.com> + +description: + The RK3576 clock controller generates the clock and also implements a reset + controller for SoC peripherals. For example it provides SCLK_UART2 and + PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART + module. + +properties: + compatible: + const: rockchip,rk3576-cru + + reg: + maxItems: 1 + + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: xin24m + - const: xin32k + +required: + - compatible + - reg + - "#clock-cells" + - "#reset-cells" + +additionalProperties: false + +examples: + - | + clock-controller@27200000 { + compatible = "rockchip,rk3576-cru"; + reg = <0xfd7c0000 0x5c000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h new file mode 100644 index 000000000000..ee3718452b77 --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h @@ -0,0 +1,592 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* +* Copyright (c) 2023 Rockchip Electronics Co. Ltd. +* Copyright (c) 2024 Collabora Ltd. +* +* Author: Elaine Zhang <zhangqing@rock-chips.com> +* Author: Detlev Casanova <detlev.casanova@collabora.com> +*/ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H + +/* cru-clocks indices */ + +/* cru plls */ +#define PLL_BPLL 0 +#define PLL_LPLL 1 +#define PLL_VPLL 2 +#define PLL_AUPLL 3 +#define PLL_CPLL 4 +#define PLL_GPLL 5 +#define PLL_PPLL 6 +#define ARMCLK_L 7 +#define ARMCLK_B 8 + +/* cru clocks */ +#define CLK_CPLL_DIV20 9 +#define CLK_CPLL_DIV10 10 +#define CLK_GPLL_DIV8 11 +#define CLK_GPLL_DIV6 12 +#define CLK_CPLL_DIV4 13 +#define CLK_GPLL_DIV4 14 +#define CLK_SPLL_DIV2 15 +#define CLK_GPLL_DIV3 16 +#define CLK_CPLL_DIV2 17 +#define CLK_GPLL_DIV2 18 +#define CLK_SPLL_DIV1 19 +#define PCLK_TOP_ROOT 20 +#define ACLK_TOP 21 +#define HCLK_TOP 22 +#define CLK_AUDIO_FRAC_0 23 +#define CLK_AUDIO_FRAC_1 24 +#define CLK_AUDIO_FRAC_2 25 +#define CLK_AUDIO_FRAC_3 26 +#define CLK_UART_FRAC_0 27 +#define CLK_UART_FRAC_1 28 +#define CLK_UART_FRAC_2 29 +#define CLK_UART1_SRC_TOP 30 +#define CLK_AUDIO_INT_0 31 +#define CLK_AUDIO_INT_1 32 +#define CLK_AUDIO_INT_2 33 +#define CLK_PDM0_SRC_TOP 34 +#define CLK_PDM1_OUT 35 +#define CLK_GMAC0_125M_SRC 36 +#define CLK_GMAC1_125M_SRC 37 +#define LCLK_ASRC_SRC_0 38 +#define LCLK_ASRC_SRC_1 39 +#define REF_CLK0_OUT_PLL 40 +#define REF_CLK1_OUT_PLL 41 +#define REF_CLK2_OUT_PLL 42 +#define REFCLKO25M_GMAC0_OUT 43 +#define REFCLKO25M_GMAC1_OUT 44 +#define CLK_CIFOUT_OUT 45 +#define CLK_GMAC0_RMII_CRU 46 +#define CLK_GMAC1_RMII_CRU 47 +#define CLK_OTPC_AUTO_RD_G 48 +#define CLK_OTP_PHY_G 49 +#define CLK_MIPI_CAMERAOUT_M0 50 +#define CLK_MIPI_CAMERAOUT_M1 51 +#define CLK_MIPI_CAMERAOUT_M2 52 +#define MCLK_PDM0_SRC_TOP 53 +#define HCLK_AUDIO_ROOT 54 +#define HCLK_ASRC_2CH_0 55 +#define HCLK_ASRC_2CH_1 56 +#define HCLK_ASRC_4CH_0 57 +#define HCLK_ASRC_4CH_1 58 +#define CLK_ASRC_2CH_0 59 +#define CLK_ASRC_2CH_1 60 +#define CLK_ASRC_4CH_0 61 +#define CLK_ASRC_4CH_1 62 +#define MCLK_SAI0_8CH_SRC 63 +#define MCLK_SAI0_8CH 64 +#define HCLK_SAI0_8CH 65 +#define HCLK_SPDIF_RX0 66 +#define MCLK_SPDIF_RX0 67 +#define HCLK_SPDIF_RX1 68 +#define MCLK_SPDIF_RX1 69 +#define MCLK_SAI1_8CH_SRC 70 +#define MCLK_SAI1_8CH 71 +#define HCLK_SAI1_8CH 72 +#define MCLK_SAI2_2CH_SRC 73 +#define MCLK_SAI2_2CH 74 +#define HCLK_SAI2_2CH 75 +#define MCLK_SAI3_2CH_SRC 76 +#define MCLK_SAI3_2CH 77 +#define HCLK_SAI3_2CH 78 +#define MCLK_SAI4_2CH_SRC 79 +#define MCLK_SAI4_2CH 80 +#define HCLK_SAI4_2CH 81 +#define HCLK_ACDCDIG_DSM 82 +#define MCLK_ACDCDIG_DSM 83 +#define CLK_PDM1 84 +#define HCLK_PDM1 85 +#define MCLK_PDM1 86 +#define HCLK_SPDIF_TX0 87 +#define MCLK_SPDIF_TX0 88 +#define HCLK_SPDIF_TX1 89 +#define MCLK_SPDIF_TX1 90 +#define CLK_SAI1_MCLKOUT 91 +#define CLK_SAI2_MCLKOUT 92 +#define CLK_SAI3_MCLKOUT 93 +#define CLK_SAI4_MCLKOUT 94 +#define CLK_SAI0_MCLKOUT 95 +#define HCLK_BUS_ROOT 96 +#define PCLK_BUS_ROOT 97 +#define ACLK_BUS_ROOT 98 +#define HCLK_CAN0 99 +#define CLK_CAN0 100 +#define HCLK_CAN1 101 +#define CLK_CAN1 102 +#define CLK_KEY_SHIFT 103 +#define PCLK_I2C1 104 +#define PCLK_I2C2 105 +#define PCLK_I2C3 106 +#define PCLK_I2C4 107 +#define PCLK_I2C5 108 +#define PCLK_I2C6 109 +#define PCLK_I2C7 110 +#define PCLK_I2C8 111 +#define PCLK_I2C9 112 +#define PCLK_WDT_BUSMCU 113 +#define TCLK_WDT_BUSMCU 114 +#define ACLK_GIC 115 +#define CLK_I2C1 116 +#define CLK_I2C2 117 +#define CLK_I2C3 118 +#define CLK_I2C4 119 +#define CLK_I2C5 120 +#define CLK_I2C6 121 +#define CLK_I2C7 122 +#define CLK_I2C8 123 +#define CLK_I2C9 124 +#define PCLK_SARADC 125 +#define CLK_SARADC 126 +#define PCLK_TSADC 127 +#define CLK_TSADC 128 +#define PCLK_UART0 129 +#define PCLK_UART2 130 +#define PCLK_UART3 131 +#define PCLK_UART4 132 +#define PCLK_UART5 133 +#define PCLK_UART6 134 +#define PCLK_UART7 135 +#define PCLK_UART8 136 +#define PCLK_UART9 137 +#define PCLK_UART10 138 +#define PCLK_UART11 139 +#define SCLK_UART0 140 +#define SCLK_UART2 141 +#define SCLK_UART3 142 +#define SCLK_UART4 143 +#define SCLK_UART5 144 +#define SCLK_UART6 145 +#define SCLK_UART7 146 +#define SCLK_UART8 147 +#define SCLK_UART9 148 +#define SCLK_UART10 149 +#define SCLK_UART11 150 +#define PCLK_SPI0 151 +#define PCLK_SPI1 152 +#define PCLK_SPI2 153 +#define PCLK_SPI3 154 +#define PCLK_SPI4 155 +#define CLK_SPI0 156 +#define CLK_SPI1 157 +#define CLK_SPI2 158 +#define CLK_SPI3 159 +#define CLK_SPI4 160 +#define PCLK_WDT0 161 +#define TCLK_WDT0 162 +#define PCLK_PWM1 163 +#define CLK_PWM1 164 +#define CLK_OSC_PWM1 165 +#define CLK_RC_PWM1 166 +#define PCLK_BUSTIMER0 167 +#define PCLK_BUSTIMER1 168 +#define CLK_TIMER0_ROOT 169 +#define CLK_TIMER0 170 +#define CLK_TIMER1 171 +#define CLK_TIMER2 172 +#define CLK_TIMER3 173 +#define CLK_TIMER4 174 +#define CLK_TIMER5 175 +#define PCLK_MAILBOX0 176 +#define PCLK_GPIO1 177 +#define DBCLK_GPIO1 178 +#define PCLK_GPIO2 179 +#define DBCLK_GPIO2 180 +#define PCLK_GPIO3 181 +#define DBCLK_GPIO3 182 +#define PCLK_GPIO4 183 +#define DBCLK_GPIO4 184 +#define ACLK_DECOM 185 +#define PCLK_DECOM 186 +#define DCLK_DECOM 187 +#define CLK_TIMER1_ROOT 188 +#define CLK_TIMER6 189 +#define CLK_TIMER7 190 +#define CLK_TIMER8 191 +#define CLK_TIMER9 192 +#define CLK_TIMER10 193 +#define CLK_TIMER11 194 +#define ACLK_DMAC0 195 +#define ACLK_DMAC1 196 +#define ACLK_DMAC2 197 +#define ACLK_SPINLOCK 198 +#define HCLK_I3C0 199 +#define HCLK_I3C1 200 +#define HCLK_BUS_CM0_ROOT 201 +#define FCLK_BUS_CM0_CORE 202 +#define CLK_BUS_CM0_RTC 203 +#define PCLK_PMU2 204 +#define PCLK_PWM2 205 +#define CLK_PWM2 206 +#define CLK_RC_PWM2 207 +#define CLK_OSC_PWM2 208 +#define CLK_FREQ_PWM1 209 +#define CLK_COUNTER_PWM1 210 +#define SAI_SCLKIN_FREQ 211 +#define SAI_SCLKIN_COUNTER 212 +#define CLK_I3C0 213 +#define CLK_I3C1 214 +#define PCLK_CSIDPHY1 215 +#define PCLK_DDR_ROOT 216 +#define PCLK_DDR_MON_CH0 217 +#define TMCLK_DDR_MON_CH0 218 +#define ACLK_DDR_ROOT 219 +#define HCLK_DDR_ROOT 220 +#define FCLK_DDR_CM0_CORE 221 +#define CLK_DDR_TIMER_ROOT 222 +#define CLK_DDR_TIMER0 223 +#define CLK_DDR_TIMER1 224 +#define TCLK_WDT_DDR 225 +#define PCLK_WDT 226 +#define PCLK_TIMER 227 +#define CLK_DDR_CM0_RTC 228 +#define ACLK_RKNN0 229 +#define ACLK_RKNN1 230 +#define HCLK_RKNN_ROOT 231 +#define CLK_RKNN_DSU0 232 +#define PCLK_NPUTOP_ROOT 233 +#define PCLK_NPU_TIMER 234 +#define CLK_NPUTIMER_ROOT 235 +#define CLK_NPUTIMER0 236 +#define CLK_NPUTIMER1 237 +#define PCLK_NPU_WDT 238 +#define TCLK_NPU_WDT 239 +#define ACLK_RKNN_CBUF 240 +#define HCLK_NPU_CM0_ROOT 241 +#define FCLK_NPU_CM0_CORE 242 +#define CLK_NPU_CM0_RTC 243 +#define HCLK_RKNN_CBUF 244 +#define HCLK_NVM_ROOT 245 +#define ACLK_NVM_ROOT 246 +#define SCLK_FSPI_X2 247 +#define HCLK_FSPI 248 +#define CCLK_SRC_EMMC 249 +#define HCLK_EMMC 250 +#define ACLK_EMMC 251 +#define BCLK_EMMC 252 +#define TCLK_EMMC 253 +#define PCLK_PHP_ROOT 254 +#define ACLK_PHP_ROOT 255 +#define PCLK_PCIE0 256 +#define CLK_PCIE0_AUX 257 +#define ACLK_PCIE0_MST 258 +#define ACLK_PCIE0_SLV 259 +#define ACLK_PCIE0_DBI 260 +#define ACLK_USB3OTG1 261 +#define CLK_REF_USB3OTG1 262 +#define CLK_SUSPEND_USB3OTG1 263 +#define ACLK_MMU0 264 +#define ACLK_SLV_MMU0 265 +#define ACLK_MMU1 266 +#define ACLK_SLV_MMU1 267 +#define PCLK_PCIE1 268 +#define CLK_PCIE1_AUX 269 +#define ACLK_PCIE1_MST 270 +#define ACLK_PCIE1_SLV 271 +#define ACLK_PCIE1_DBI 272 +#define CLK_RXOOB0 273 +#define CLK_RXOOB1 274 +#define CLK_PMALIVE0 275 +#define CLK_PMALIVE1 276 +#define ACLK_SATA0 277 +#define ACLK_SATA1 278 +#define CLK_USB3OTG1_PIPE_PCLK 279 +#define CLK_USB3OTG1_UTMI 280 +#define CLK_USB3OTG0_PIPE_PCLK 281 +#define CLK_USB3OTG0_UTMI 282 +#define HCLK_SDGMAC_ROOT 283 +#define ACLK_SDGMAC_ROOT 284 +#define PCLK_SDGMAC_ROOT 285 +#define ACLK_GMAC0 286 +#define ACLK_GMAC1 287 +#define PCLK_GMAC0 288 +#define PCLK_GMAC1 289 +#define CCLK_SRC_SDIO 290 +#define HCLK_SDIO 291 +#define CLK_GMAC1_PTP_REF 292 +#define CLK_GMAC0_PTP_REF 293 +#define CLK_GMAC1_PTP_REF_SRC 294 +#define CLK_GMAC0_PTP_REF_SRC 295 +#define CCLK_SRC_SDMMC0 296 +#define HCLK_SDMMC0 297 +#define SCLK_FSPI1_X2 298 +#define HCLK_FSPI1 299 +#define ACLK_DSMC_ROOT 300 +#define ACLK_DSMC 301 +#define PCLK_DSMC 302 +#define CLK_DSMC_SYS 303 +#define HCLK_HSGPIO 304 +#define CLK_HSGPIO_TX 305 +#define CLK_HSGPIO_RX 306 +#define ACLK_HSGPIO 307 +#define PCLK_PHPPHY_ROOT 308 +#define PCLK_PCIE2_COMBOPHY0 309 +#define PCLK_PCIE2_COMBOPHY1 310 +#define CLK_PCIE_100M_SRC 311 +#define CLK_PCIE_100M_NDUTY_SRC 312 +#define CLK_REF_PCIE0_PHY 313 +#define CLK_REF_PCIE1_PHY 314 +#define CLK_REF_MPHY_26M 315 +#define HCLK_RKVDEC_ROOT 316 +#define ACLK_RKVDEC_ROOT 317 +#define HCLK_RKVDEC 318 +#define CLK_RKVDEC_HEVC_CA 319 +#define CLK_RKVDEC_CORE 320 +#define ACLK_UFS_ROOT 321 +#define ACLK_USB_ROOT 322 +#define PCLK_USB_ROOT 323 +#define ACLK_USB3OTG0 324 +#define CLK_REF_USB3OTG0 325 +#define CLK_SUSPEND_USB3OTG0 326 +#define ACLK_MMU2 327 +#define ACLK_SLV_MMU2 328 +#define ACLK_UFS_SYS 329 +#define ACLK_VPU_ROOT 330 +#define ACLK_VPU_MID_ROOT 331 +#define HCLK_VPU_ROOT 332 +#define ACLK_JPEG_ROOT 333 +#define ACLK_VPU_LOW_ROOT 334 +#define HCLK_RGA2E_0 335 +#define ACLK_RGA2E_0 336 +#define CLK_CORE_RGA2E_0 337 +#define ACLK_JPEG 338 +#define HCLK_JPEG 339 +#define HCLK_VDPP 340 +#define ACLK_VDPP 341 +#define CLK_CORE_VDPP 342 +#define HCLK_RGA2E_1 343 +#define ACLK_RGA2E_1 344 +#define CLK_CORE_RGA2E_1 345 +#define DCLK_EBC_FRAC_SRC 346 +#define HCLK_EBC 347 +#define ACLK_EBC 348 +#define DCLK_EBC 349 +#define HCLK_VEPU0_ROOT 350 +#define ACLK_VEPU0_ROOT 351 +#define HCLK_VEPU0 352 +#define ACLK_VEPU0 353 +#define CLK_VEPU0_CORE 354 +#define ACLK_VI_ROOT 355 +#define HCLK_VI_ROOT 356 +#define PCLK_VI_ROOT 357 +#define DCLK_VICAP 358 +#define ACLK_VICAP 359 +#define HCLK_VICAP 360 +#define CLK_ISP_CORE 361 +#define CLK_ISP_CORE_MARVIN 362 +#define CLK_ISP_CORE_VICAP 363 +#define ACLK_ISP 364 +#define HCLK_ISP 365 +#define ACLK_VPSS 366 +#define HCLK_VPSS 367 +#define CLK_CORE_VPSS 368 +#define PCLK_CSI_HOST_0 369 +#define PCLK_CSI_HOST_1 370 +#define PCLK_CSI_HOST_2 371 +#define PCLK_CSI_HOST_3 372 +#define PCLK_CSI_HOST_4 373 +#define ICLK_CSIHOST01 374 +#define ICLK_CSIHOST0 375 +#define CLK_ISP_PVTPLL_SRC 376 +#define ACLK_VI_ROOT_INTER 377 +#define CLK_VICAP_I0CLK 378 +#define CLK_VICAP_I1CLK 379 +#define CLK_VICAP_I2CLK 380 +#define CLK_VICAP_I3CLK 381 +#define CLK_VICAP_I4CLK 382 +#define ACLK_VOP_ROOT 383 +#define HCLK_VOP_ROOT 384 +#define PCLK_VOP_ROOT 385 +#define HCLK_VOP 386 +#define ACLK_VOP 387 +#define DCLK_VP0_SRC 388 +#define DCLK_VP1_SRC 389 +#define DCLK_VP2_SRC 390 +#define DCLK_VP0 391 +#define DCLK_VP1 392 +#define DCLK_VP2 393 +#define PCLK_VOPGRF 394 +#define ACLK_VO0_ROOT 395 +#define HCLK_VO0_ROOT 396 +#define PCLK_VO0_ROOT 397 +#define PCLK_VO0_GRF 398 +#define ACLK_HDCP0 399 +#define HCLK_HDCP0 400 +#define PCLK_HDCP0 401 +#define CLK_TRNG0_SKP 402 +#define PCLK_DSIHOST0 403 +#define CLK_DSIHOST0 404 +#define PCLK_HDMITX0 405 +#define CLK_HDMITX0_EARC 406 +#define CLK_HDMITX0_REF 407 +#define PCLK_EDP0 408 +#define CLK_EDP0_24M 409 +#define CLK_EDP0_200M 410 +#define MCLK_SAI5_8CH_SRC 411 +#define MCLK_SAI5_8CH 412 +#define HCLK_SAI5_8CH 413 +#define MCLK_SAI6_8CH_SRC 414 +#define MCLK_SAI6_8CH 415 +#define HCLK_SAI6_8CH 416 +#define HCLK_SPDIF_TX2 417 +#define MCLK_SPDIF_TX2 418 +#define HCLK_SPDIF_RX2 419 +#define MCLK_SPDIF_RX2 420 +#define HCLK_SAI8_8CH 421 +#define MCLK_SAI8_8CH_SRC 422 +#define MCLK_SAI8_8CH 423 +#define ACLK_VO1_ROOT 424 +#define HCLK_VO1_ROOT 425 +#define PCLK_VO1_ROOT 426 +#define MCLK_SAI7_8CH_SRC 427 +#define MCLK_SAI7_8CH 428 +#define HCLK_SAI7_8CH 429 +#define HCLK_SPDIF_TX3 430 +#define HCLK_SPDIF_TX4 431 +#define HCLK_SPDIF_TX5 432 +#define MCLK_SPDIF_TX3 433 +#define CLK_AUX16MHZ_0 434 +#define ACLK_DP0 435 +#define PCLK_DP0 436 +#define PCLK_VO1_GRF 437 +#define ACLK_HDCP1 438 +#define HCLK_HDCP1 439 +#define PCLK_HDCP1 440 +#define CLK_TRNG1_SKP 441 +#define HCLK_SAI9_8CH 442 +#define MCLK_SAI9_8CH_SRC 443 +#define MCLK_SAI9_8CH 444 +#define MCLK_SPDIF_TX4 445 +#define MCLK_SPDIF_TX5 446 +#define CLK_GPU_SRC_PRE 447 +#define CLK_GPU 448 +#define PCLK_GPU_ROOT 449 +#define ACLK_CENTER_ROOT 450 +#define ACLK_CENTER_LOW_ROOT 451 +#define HCLK_CENTER_ROOT 452 +#define PCLK_CENTER_ROOT 453 +#define ACLK_DMA2DDR 454 +#define ACLK_DDR_SHAREMEM 455 +#define PCLK_DMA2DDR 456 +#define PCLK_SHAREMEM 457 +#define HCLK_VEPU1_ROOT 458 +#define ACLK_VEPU1_ROOT 459 +#define HCLK_VEPU1 460 +#define ACLK_VEPU1 461 +#define CLK_VEPU1_CORE 462 +#define CLK_JDBCK_DAP 463 +#define PCLK_MIPI_DCPHY 464 +#define CLK_32K_USB2DEBUG 465 +#define PCLK_CSIDPHY 466 +#define PCLK_USBDPPHY 467 +#define CLK_PMUPHY_REF_SRC 468 +#define CLK_USBDP_COMBO_PHY_IMMORTAL 469 +#define CLK_HDMITXHPD 470 +#define PCLK_MPHY 471 +#define CLK_REF_OSC_MPHY 472 +#define CLK_REF_UFS_CLKOUT 473 +#define HCLK_PMU1_ROOT 474 +#define HCLK_PMU_CM0_ROOT 475 +#define CLK_200M_PMU_SRC 476 +#define CLK_100M_PMU_SRC 477 +#define CLK_50M_PMU_SRC 478 +#define FCLK_PMU_CM0_CORE 479 +#define CLK_PMU_CM0_RTC 480 +#define PCLK_PMU1 481 +#define CLK_PMU1 482 +#define PCLK_PMU1WDT 483 +#define TCLK_PMU1WDT 484 +#define PCLK_PMUTIMER 485 +#define CLK_PMUTIMER_ROOT 486 +#define CLK_PMUTIMER0 487 +#define CLK_PMUTIMER1 488 +#define PCLK_PMU1PWM 489 +#define CLK_PMU1PWM 490 +#define CLK_PMU1PWM_OSC 491 +#define PCLK_PMUPHY_ROOT 492 +#define PCLK_I2C0 493 +#define CLK_I2C0 494 +#define SCLK_UART1 495 +#define PCLK_UART1 496 +#define CLK_PMU1PWM_RC 497 +#define CLK_PDM0 498 +#define HCLK_PDM0 499 +#define MCLK_PDM0 500 +#define HCLK_VAD 501 +#define CLK_OSCCHK_PVTM 502 +#define CLK_PDM0_OUT 503 +#define CLK_HPTIMER_SRC 504 +#define PCLK_PMU0_ROOT 505 +#define PCLK_PMU0 506 +#define PCLK_GPIO0 507 +#define DBCLK_GPIO0 508 +#define CLK_OSC0_PMU1 509 +#define PCLK_PMU1_ROOT 510 +#define XIN_OSC0_DIV 511 +#define ACLK_USB 512 +#define ACLK_UFS 513 +#define ACLK_SDGMAC 514 +#define HCLK_SDGMAC 515 +#define PCLK_SDGMAC 516 +#define HCLK_VO1 517 +#define HCLK_VO0 518 +#define PCLK_CCI_ROOT 519 +#define ACLK_CCI_ROOT 520 +#define HCLK_VO0VOP_CHANNEL 521 +#define ACLK_VO0VOP_CHANNEL 522 +#define ACLK_TOP_MID 523 +#define ACLK_SECURE_HIGH 524 +#define CLK_USBPHY_REF_SRC 525 +#define CLK_PHY_REF_SRC 526 +#define CLK_CPLL_REF_SRC 527 +#define CLK_AUPLL_REF_SRC 528 +#define PCLK_SECURE_NS 529 +#define HCLK_SECURE_NS 530 +#define ACLK_SECURE_NS 531 +#define PCLK_OTPC_NS 532 +#define HCLK_CRYPTO_NS 533 +#define HCLK_TRNG_NS 534 +#define CLK_OTPC_NS 535 +#define SCLK_DSU 536 +#define SCLK_DDR 537 +#define ACLK_CRYPTO_NS 538 +#define CLK_PKA_CRYPTO_NS 539 +#define ACLK_RKVDEC_ROOT_BAK 540 +#define CLK_AUDIO_FRAC_0_SRC 541 +#define CLK_AUDIO_FRAC_1_SRC 542 +#define CLK_AUDIO_FRAC_2_SRC 543 +#define CLK_AUDIO_FRAC_3_SRC 544 +#define PCLK_HDPTX_APB 545 + +/* secure clk */ +#define CLK_STIMER0_ROOT 546 +#define CLK_STIMER1_ROOT 547 +#define PCLK_SECURE_S 548 +#define HCLK_SECURE_S 549 +#define ACLK_SECURE_S 550 +#define CLK_PKA_CRYPTO_S 551 +#define HCLK_VO1_S 552 +#define PCLK_VO1_S 553 +#define HCLK_VO0_S 554 +#define PCLK_VO0_S 555 +#define PCLK_KLAD 556 +#define HCLK_CRYPTO_S 557 +#define HCLK_KLAD 558 +#define ACLK_CRYPTO_S 559 +#define HCLK_TRNG_S 560 +#define PCLK_OTPC_S 561 +#define CLK_OTPC_S 562 +#define PCLK_WDT_S 563 +#define TCLK_WDT_S 564 +#define PCLK_HDCP0_TRNG 565 +#define PCLK_HDCP1_TRNG 566 +#define HCLK_HDCP_KEY0 567 +#define HCLK_HDCP_KEY1 568 +#define PCLK_EDP_S 569 +#define ACLK_KLAD 570 + +#endif diff --git a/include/dt-bindings/reset/rockchip,rk3576-cru.h b/include/dt-bindings/reset/rockchip,rk3576-cru.h new file mode 100644 index 000000000000..8c968af4888d --- /dev/null +++ b/include/dt-bindings/reset/rockchip,rk3576-cru.h @@ -0,0 +1,564 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* +* Copyright (c) 2023 Rockchip Electronics Co. Ltd. +* Copyright (c) 2024 Collabora Ltd. +* +* Author: Elaine Zhang <zhangqing@rock-chips.com> +* Author: Detlev Casanova <detlev.casanova@collabora.com> +*/ + +#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H +#define _DT_BINDINGS_RESET_ROCKCHIP_RK3576_H + +#define SRST_A_TOP_BIU 0 +#define SRST_P_TOP_BIU 1 +#define SRST_A_TOP_MID_BIU 2 +#define SRST_A_SECURE_HIGH_BIU 3 +#define SRST_H_TOP_BIU 4 + +#define SRST_H_VO0VOP_CHANNEL_BIU 5 +#define SRST_A_VO0VOP_CHANNEL_BIU 6 + +#define SRST_BISRINTF 7 + +#define SRST_H_AUDIO_BIU 8 +#define SRST_H_ASRC_2CH_0 9 +#define SRST_H_ASRC_2CH_1 10 +#define SRST_H_ASRC_4CH_0 11 +#define SRST_H_ASRC_4CH_1 12 +#define SRST_ASRC_2CH_0 13 +#define SRST_ASRC_2CH_1 14 +#define SRST_ASRC_4CH_0 15 +#define SRST_ASRC_4CH_1 16 +#define SRST_M_SAI0_8CH 17 +#define SRST_H_SAI0_8CH 18 +#define SRST_H_SPDIF_RX0 19 +#define SRST_M_SPDIF_RX0 20 + +#define SRST_H_SPDIF_RX1 21 +#define SRST_M_SPDIF_RX1 22 +#define SRST_M_SAI1_8CH 23 +#define SRST_H_SAI1_8CH 24 +#define SRST_M_SAI2_2CH 25 +#define SRST_H_SAI2_2CH 26 +#define SRST_M_SAI3_2CH 27 +#define SRST_H_SAI3_2CH 28 + +#define SRST_M_SAI4_2CH 29 +#define SRST_H_SAI4_2CH 30 +#define SRST_H_ACDCDIG_DSM 31 +#define SRST_M_ACDCDIG_DSM 32 +#define SRST_PDM1 33 +#define SRST_H_PDM1 34 +#define SRST_M_PDM1 35 +#define SRST_H_SPDIF_TX0 36 +#define SRST_M_SPDIF_TX0 37 +#define SRST_H_SPDIF_TX1 38 +#define SRST_M_SPDIF_TX1 39 + +#define SRST_A_BUS_BIU 40 +#define SRST_P_BUS_BIU 41 +#define SRST_P_CRU 42 +#define SRST_H_CAN0 43 +#define SRST_CAN0 44 +#define SRST_H_CAN1 45 +#define SRST_CAN1 46 +#define SRST_P_INTMUX2BUS 47 +#define SRST_P_VCCIO_IOC 48 +#define SRST_H_BUS_BIU 49 +#define SRST_KEY_SHIFT 50 + +#define SRST_P_I2C1 51 +#define SRST_P_I2C2 52 +#define SRST_P_I2C3 53 +#define SRST_P_I2C4 54 +#define SRST_P_I2C5 55 +#define SRST_P_I2C6 56 +#define SRST_P_I2C7 57 +#define SRST_P_I2C8 58 +#define SRST_P_I2C9 59 +#define SRST_P_WDT_BUSMCU 60 +#define SRST_T_WDT_BUSMCU 61 +#define SRST_A_GIC 62 +#define SRST_I2C1 63 +#define SRST_I2C2 64 +#define SRST_I2C3 65 +#define SRST_I2C4 66 + +#define SRST_I2C5 67 +#define SRST_I2C6 68 +#define SRST_I2C7 69 +#define SRST_I2C8 70 +#define SRST_I2C9 71 +#define SRST_P_SARADC 72 +#define SRST_SARADC 73 +#define SRST_P_TSADC 74 +#define SRST_TSADC 75 +#define SRST_P_UART0 76 +#define SRST_P_UART2 77 +#define SRST_P_UART3 78 +#define SRST_P_UART4 79 +#define SRST_P_UART5 80 +#define SRST_P_UART6 81 + +#define SRST_P_UART7 82 +#define SRST_P_UART8 83 +#define SRST_P_UART9 84 +#define SRST_P_UART10 85 +#define SRST_P_UART11 86 +#define SRST_S_UART0 87 +#define SRST_S_UART2 88 +#define SRST_S_UART3 89 +#define SRST_S_UART4 90 +#define SRST_S_UART5 91 + +#define SRST_S_UART6 92 +#define SRST_S_UART7 93 +#define SRST_S_UART8 94 +#define SRST_S_UART9 95 +#define SRST_S_UART10 96 +#define SRST_S_UART11 97 +#define SRST_P_SPI0 98 +#define SRST_P_SPI1 99 +#define SRST_P_SPI2 100 + +#define SRST_P_SPI3 101 +#define SRST_P_SPI4 102 +#define SRST_SPI0 103 +#define SRST_SPI1 104 +#define SRST_SPI2 105 +#define SRST_SPI3 106 +#define SRST_SPI4 107 +#define SRST_P_WDT0 108 +#define SRST_T_WDT0 109 +#define SRST_P_SYS_GRF 110 +#define SRST_P_PWM1 111 +#define SRST_PWM1 112 + +#define SRST_P_BUSTIMER0 113 +#define SRST_P_BUSTIMER1 114 +#define SRST_TIMER0 115 +#define SRST_TIMER1 116 +#define SRST_TIMER2 117 +#define SRST_TIMER3 118 +#define SRST_TIMER4 119 +#define SRST_TIMER5 120 +#define SRST_P_BUSIOC 121 +#define SRST_P_MAILBOX0 122 +#define SRST_P_GPIO1 123 + +#define SRST_GPIO1 124 +#define SRST_P_GPIO2 125 +#define SRST_GPIO2 126 +#define SRST_P_GPIO3 127 +#define SRST_GPIO3 128 +#define SRST_P_GPIO4 129 +#define SRST_GPIO4 130 +#define SRST_A_DECOM 131 +#define SRST_P_DECOM 132 +#define SRST_D_DECOM 133 +#define SRST_TIMER6 134 +#define SRST_TIMER7 135 +#define SRST_TIMER8 136 +#define SRST_TIMER9 137 +#define SRST_TIMER10 138 + +#define SRST_TIMER11 139 +#define SRST_A_DMAC0 140 +#define SRST_A_DMAC1 141 +#define SRST_A_DMAC2 142 +#define SRST_A_SPINLOCK 143 +#define SRST_REF_PVTPLL_BUS 144 +#define SRST_H_I3C0 145 +#define SRST_H_I3C1 146 +#define SRST_H_BUS_CM0_BIU 147 +#define SRST_F_BUS_CM0_CORE 148 +#define SRST_T_BUS_CM0_JTAG 149 + +#define SRST_P_INTMUX2PMU 150 +#define SRST_P_INTMUX2DDR 151 +#define SRST_P_PVTPLL_BUS 152 +#define SRST_P_PWM2 153 +#define SRST_PWM2 154 +#define SRST_FREQ_PWM1 155 +#define SRST_COUNTER_PWM1 156 +#define SRST_I3C0 157 +#define SRST_I3C1 158 + +#define SRST_P_DDR_MON_CH0 159 +#define SRST_P_DDR_BIU 160 +#define SRST_P_DDR_UPCTL_CH0 161 +#define SRST_TM_DDR_MON_CH0 162 +#define SRST_A_DDR_BIU 163 +#define SRST_DFI_CH0 164 +#define SRST_DDR_MON_CH0 165 +#define SRST_P_DDR_HWLP_CH0 166 +#define SRST_P_DDR_MON_CH1 167 +#define SRST_P_DDR_HWLP_CH1 168 + +#define SRST_P_DDR_UPCTL_CH1 169 +#define SRST_TM_DDR_MON_CH1 170 +#define SRST_DFI_CH1 171 +#define SRST_A_DDR01_MSCH0 172 +#define SRST_A_DDR01_MSCH1 173 +#define SRST_DDR_MON_CH1 174 +#define SRST_DDR_SCRAMBLE_CH0 175 +#define SRST_DDR_SCRAMBLE_CH1 176 +#define SRST_P_AHB2APB 177 +#define SRST_H_AHB2APB 178 +#define SRST_H_DDR_BIU 179 +#define SRST_F_DDR_CM0_CORE 180 + +#define SRST_P_DDR01_MSCH0 181 +#define SRST_P_DDR01_MSCH1 182 +#define SRST_DDR_TIMER0 183 +#define SRST_DDR_TIMER1 184 +#define SRST_T_WDT_DDR 185 +#define SRST_P_WDT 186 +#define SRST_P_TIMER 187 +#define SRST_T_DDR_CM0_JTAG 188 +#define SRST_P_DDR_GRF 189 + +#define SRST_DDR_UPCTL_CH0 190 +#define SRST_A_DDR_UPCTL_0_CH0 191 +#define SRST_A_DDR_UPCTL_1_CH0 192 +#define SRST_A_DDR_UPCTL_2_CH0 193 +#define SRST_A_DDR_UPCTL_3_CH0 194 +#define SRST_A_DDR_UPCTL_4_CH0 195 + +#define SRST_DDR_UPCTL_CH1 196 +#define SRST_A_DDR_UPCTL_0_CH1 197 +#define SRST_A_DDR_UPCTL_1_CH1 198 +#define SRST_A_DDR_UPCTL_2_CH1 199 +#define SRST_A_DDR_UPCTL_3_CH1 200 +#define SRST_A_DDR_UPCTL_4_CH1 201 + +#define SRST_REF_PVTPLL_DDR 202 +#define SRST_P_PVTPLL_DDR 203 + +#define SRST_A_RKNN0 204 +#define SRST_A_RKNN0_BIU 205 +#define SRST_L_RKNN0_BIU 206 + +#define SRST_A_RKNN1 207 +#define SRST_A_RKNN1_BIU 208 +#define SRST_L_RKNN1_BIU 209 + +#define SRST_NPU_DAP 210 +#define SRST_L_NPUSUBSYS_BIU 211 +#define SRST_P_NPUTOP_BIU 212 +#define SRST_P_NPU_TIMER 213 +#define SRST_NPUTIMER0 214 +#define SRST_NPUTIMER1 215 +#define SRST_P_NPU_WDT 216 +#define SRST_T_NPU_WDT 217 + +#define SRST_A_RKNN_CBUF 218 +#define SRST_A_RVCORE0 219 +#define SRST_P_NPU_GRF 220 +#define SRST_P_PVTPLL_NPU 221 +#define SRST_NPU_PVTPLL 222 +#define SRST_H_NPU_CM0_BIU 223 +#define SRST_F_NPU_CM0_CORE 224 +#define SRST_T_NPU_CM0_JTAG 225 +#define SRST_A_RKNNTOP_BIU 226 +#define SRST_H_RKNN_CBUF 227 +#define SRST_H_RKNNTOP_BIU 228 + +#define SRST_H_NVM_BIU 229 +#define SRST_A_NVM_BIU 230 +#define SRST_S_FSPI 231 +#define SRST_H_FSPI 232 +#define SRST_C_EMMC 233 +#define SRST_H_EMMC 234 +#define SRST_A_EMMC 235 +#define SRST_B_EMMC 236 +#define SRST_T_EMMC 237 + +#define SRST_P_GRF 238 +#define SRST_P_PHP_BIU 239 +#define SRST_A_PHP_BIU 240 +#define SRST_P_PCIE0 241 +#define SRST_PCIE0_POWER_UP 242 + +#define SRST_A_USB3OTG1 243 +#define SRST_A_MMU0 244 +#define SRST_A_SLV_MMU0 245 +#define SRST_A_MMU1 246 + +#define SRST_A_SLV_MMU1 247 +#define SRST_P_PCIE1 248 +#define SRST_PCIE1_POWER_UP 249 + +#define SRST_RXOOB0 250 +#define SRST_RXOOB1 251 +#define SRST_PMALIVE0 252 +#define SRST_PMALIVE1 253 +#define SRST_A_SATA0 254 +#define SRST_A_SATA1 255 +#define SRST_ASIC1 256 +#define SRST_ASIC0 257 + +#define SRST_P_CSIDPHY1 258 +#define SRST_SCAN_CSIDPHY1 259 + +#define SRST_P_SDGMAC_GRF 260 +#define SRST_P_SDGMAC_BIU 261 +#define SRST_A_SDGMAC_BIU 262 +#define SRST_H_SDGMAC_BIU 263 +#define SRST_A_GMAC0 264 +#define SRST_A_GMAC1 265 +#define SRST_P_GMAC0 266 +#define SRST_P_GMAC1 267 +#define SRST_H_SDIO 268 + +#define SRST_H_SDMMC0 269 +#define SRST_S_FSPI1 270 +#define SRST_H_FSPI1 271 +#define SRST_A_DSMC_BIU 272 +#define SRST_A_DSMC 273 +#define SRST_P_DSMC 274 +#define SRST_H_HSGPIO 275 +#define SRST_HSGPIO 276 +#define SRST_A_HSGPIO 277 + +#define SRST_H_RKVDEC 278 +#define SRST_H_RKVDEC_BIU 279 +#define SRST_A_RKVDEC_BIU 280 +#define SRST_RKVDEC_HEVC_CA 281 +#define SRST_RKVDEC_CORE 282 + +#define SRST_A_USB_BIU 283 +#define SRST_P_USBUFS_BIU 284 +#define SRST_A_USB3OTG0 285 +#define SRST_A_UFS_BIU 286 +#define SRST_A_MMU2 287 +#define SRST_A_SLV_MMU2 288 +#define SRST_A_UFS_SYS 289 + +#define SRST_A_UFS 290 +#define SRST_P_USBUFS_GRF 291 +#define SRST_P_UFS_GRF 292 + +#define SRST_H_VPU_BIU 293 +#define SRST_A_JPEG_BIU 294 +#define SRST_A_RGA_BIU 295 +#define SRST_A_VDPP_BIU 296 +#define SRST_A_EBC_BIU 297 +#define SRST_H_RGA2E_0 298 +#define SRST_A_RGA2E_0 299 +#define SRST_CORE_RGA2E_0 300 + +#define SRST_A_JPEG 301 +#define SRST_H_JPEG 302 +#define SRST_H_VDPP 303 +#define SRST_A_VDPP 304 +#define SRST_CORE_VDPP 305 +#define SRST_H_RGA2E_1 306 +#define SRST_A_RGA2E_1 307 +#define SRST_CORE_RGA2E_1 308 +#define SRST_H_EBC 309 +#define SRST_A_EBC 310 +#define SRST_D_EBC 311 + +#define SRST_H_VEPU0_BIU 312 +#define SRST_A_VEPU0_BIU 313 +#define SRST_H_VEPU0 314 +#define SRST_A_VEPU0 315 +#define SRST_VEPU0_CORE 316 + +#define SRST_A_VI_BIU 317 +#define SRST_H_VI_BIU 318 +#define SRST_P_VI_BIU 319 +#define SRST_D_VICAP 320 +#define SRST_A_VICAP 321 +#define SRST_H_VICAP 322 +#define SRST_ISP0 323 +#define SRST_ISP0_VICAP 324 + +#define SRST_CORE_VPSS 325 +#define SRST_P_CSI_HOST_0 326 +#define SRST_P_CSI_HOST_1 327 +#define SRST_P_CSI_HOST_2 328 +#define SRST_P_CSI_HOST_3 329 +#define SRST_P_CSI_HOST_4 330 + +#define SRST_CIFIN 331 +#define SRST_VICAP_I0CLK 332 +#define SRST_VICAP_I1CLK 333 +#define SRST_VICAP_I2CLK 334 +#define SRST_VICAP_I3CLK 335 +#define SRST_VICAP_I4CLK 336 + +#define SRST_A_VOP_BIU 337 +#define SRST_A_VOP2_BIU 338 +#define SRST_H_VOP_BIU 339 +#define SRST_P_VOP_BIU 340 +#define SRST_H_VOP 341 +#define SRST_A_VOP 342 +#define SRST_D_VP0 343 + +#define SRST_D_VP1 344 +#define SRST_D_VP2 345 +#define SRST_P_VOP2_BIU 346 +#define SRST_P_VOPGRF 347 + +#define SRST_H_VO0_BIU 348 +#define SRST_P_VO0_BIU 349 +#define SRST_A_HDCP0_BIU 350 +#define SRST_P_VO0_GRF 351 +#define SRST_A_HDCP0 352 +#define SRST_H_HDCP0 353 +#define SRST_HDCP0 354 + +#define SRST_P_DSIHOST0 355 +#define SRST_DSIHOST0 356 +#define SRST_P_HDMITX0 357 +#define SRST_HDMITX0_REF 358 +#define SRST_P_EDP0 359 +#define SRST_EDP0_24M 360 + +#define SRST_M_SAI5_8CH 361 +#define SRST_H_SAI5_8CH 362 +#define SRST_M_SAI6_8CH 363 +#define SRST_H_SAI6_8CH 364 +#define SRST_H_SPDIF_TX2 365 +#define SRST_M_SPDIF_TX2 366 +#define SRST_H_SPDIF_RX2 367 +#define SRST_M_SPDIF_RX2 368 + +#define SRST_H_SAI8_8CH 369 +#define SRST_M_SAI8_8CH 370 + +#define SRST_H_VO1_BIU 371 +#define SRST_P_VO1_BIU 372 +#define SRST_M_SAI7_8CH 373 +#define SRST_H_SAI7_8CH 374 +#define SRST_H_SPDIF_TX3 375 +#define SRST_H_SPDIF_TX4 376 +#define SRST_H_SPDIF_TX5 377 +#define SRST_M_SPDIF_TX3 378 + +#define SRST_DP0 379 +#define SRST_P_VO1_GRF 380 +#define SRST_A_HDCP1_BIU 381 +#define SRST_A_HDCP1 382 +#define SRST_H_HDCP1 383 +#define SRST_HDCP1 384 +#define SRST_H_SAI9_8CH 385 +#define SRST_M_SAI9_8CH 386 +#define SRST_M_SPDIF_TX4 387 +#define SRST_M_SPDIF_TX5 388 + +#define SRST_GPU 389 +#define SRST_A_S_GPU_BIU 390 +#define SRST_A_M0_GPU_BIU 391 +#define SRST_P_GPU_BIU 392 +#define SRST_P_GPU_GRF 393 +#define SRST_GPU_PVTPLL 394 +#define SRST_P_PVTPLL_GPU 395 + +#define SRST_A_CENTER_BIU 396 +#define SRST_A_DMA2DDR 397 +#define SRST_A_DDR_SHAREMEM 398 +#define SRST_A_DDR_SHAREMEM_BIU 399 +#define SRST_H_CENTER_BIU 400 +#define SRST_P_CENTER_GRF 401 +#define SRST_P_DMA2DDR 402 +#define SRST_P_SHAREMEM 403 +#define SRST_P_CENTER_BIU 404 + +#define SRST_LINKSYM_HDMITXPHY0 405 + +#define SRST_DP0_PIXELCLK 406 +#define SRST_PHY_DP0_TX 407 +#define SRST_DP1_PIXELCLK 408 +#define SRST_DP2_PIXELCLK 409 + +#define SRST_H_VEPU1_BIU 410 +#define SRST_A_VEPU1_BIU 411 +#define SRST_H_VEPU1 412 +#define SRST_A_VEPU1 413 +#define SRST_VEPU1_CORE 414 + +#define SRST_P_PHPPHY_CRU 415 +#define SRST_P_APB2ASB_SLV_CHIP_TOP 416 +#define SRST_P_PCIE2_COMBOPHY0 417 +#define SRST_P_PCIE2_COMBOPHY0_GRF 418 +#define SRST_P_PCIE2_COMBOPHY1 419 +#define SRST_P_PCIE2_COMBOPHY1_GRF 420 + +#define SRST_PCIE0_PIPE_PHY 421 +#define SRST_PCIE1_PIPE_PHY 422 + +#define SRST_H_CRYPTO_NS 423 +#define SRST_H_TRNG_NS 424 +#define SRST_P_OTPC_NS 425 +#define SRST_OTPC_NS 426 + +#define SRST_P_HDPTX_GRF 427 +#define SRST_P_HDPTX_APB 428 +#define SRST_P_MIPI_DCPHY 429 +#define SRST_P_DCPHY_GRF 430 +#define SRST_P_BOT0_APB2ASB 431 +#define SRST_P_BOT1_APB2ASB 432 +#define SRST_USB2DEBUG 433 +#define SRST_P_CSIPHY_GRF 434 +#define SRST_P_CSIPHY 435 +#define SRST_P_USBPHY_GRF_0 436 +#define SRST_P_USBPHY_GRF_1 437 +#define SRST_P_USBDP_GRF 438 +#define SRST_P_USBDPPHY 439 +#define SRST_USBDP_COMBO_PHY_INIT 440 + +#define SRST_USBDP_COMBO_PHY_CMN 441 +#define SRST_USBDP_COMBO_PHY_LANE 442 +#define SRST_USBDP_COMBO_PHY_PCS 443 +#define SRST_M_MIPI_DCPHY 444 +#define SRST_S_MIPI_DCPHY 445 +#define SRST_SCAN_CSIPHY 446 +#define SRST_P_VCCIO6_IOC 447 +#define SRST_OTGPHY_0 448 +#define SRST_OTGPHY_1 449 +#define SRST_HDPTX_INIT 450 +#define SRST_HDPTX_CMN 451 +#define SRST_HDPTX_LANE 452 +#define SRST_HDMITXHPD 453 + +#define SRST_MPHY_INIT 454 +#define SRST_P_MPHY_GRF 455 +#define SRST_P_VCCIO7_IOC 456 + +#define SRST_H_PMU1_BIU 457 +#define SRST_P_PMU1_NIU 458 +#define SRST_H_PMU_CM0_BIU 459 +#define SRST_PMU_CM0_CORE 460 +#define SRST_PMU_CM0_JTAG 461 + +#define SRST_P_CRU_PMU1 462 +#define SRST_P_PMU1_GRF 463 +#define SRST_P_PMU1_IOC 464 +#define SRST_P_PMU1WDT 465 +#define SRST_T_PMU1WDT 466 +#define SRST_P_PMUTIMER 467 +#define SRST_PMUTIMER0 468 +#define SRST_PMUTIMER1 469 +#define SRST_P_PMU1PWM 470 +#define SRST_PMU1PWM 471 + +#define SRST_P_I2C0 472 +#define SRST_I2C0 473 +#define SRST_S_UART1 474 +#define SRST_P_UART1 475 +#define SRST_PDM0 476 +#define SRST_H_PDM0 477 + +#define SRST_M_PDM0 478 +#define SRST_H_VAD 479 + +#define SRST_P_PMU0GRF 480 +#define SRST_P_PMU0IOC 481 +#define SRST_P_GPIO0 482 +#define SRST_DB_GPIO0 483 + +#endif -- 2.46.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re:[PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova @ 2024-08-26 11:04 ` Andy Yan 2024-08-26 14:00 ` [PATCH " Rob Herring (Arm) 1 sibling, 0 replies; 8+ messages in thread From: Andy Yan @ 2024-08-26 11:04 UTC (permalink / raw) To: Detlev Casanova Cc: linux-kernel, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel, Sugar Zhang Hi Deltev， Thanks for your work。 At 2024-08-23 03:49:32, "Detlev Casanova" <detlev.casanova@collabora.com> wrote: >Add clock and reset ID defines for rk3576. > >Compared to the downstream bindings written by Elaine, this uses >continous gapless IDs starting at 0. Thus all numbers are >different between downstream and upstream, but names are kept >exactly the same. > >Also add documentation for the rk3576 CRU core. > >Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> >Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> >Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> >--- > .../bindings/clock/rockchip,rk3576-cru.yaml | 56 ++ > .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++ > .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++ > 3 files changed, 1212 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml > create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h > create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h > >diff --git a/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml >new file mode 100644 >index 000000000000..9c9b36049c71 >--- /dev/null >+++ b/Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml >@@ -0,0 +1,56 @@ >+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause >+%YAML 1.2 >+--- >+$id: http://devicetree.org/schemas/clock/rockchip,rk3576-cru.yaml# >+$schema: http://devicetree.org/meta-schemas/core.yaml# >+ >+title: Rockchip rk3576 Family Clock and Reset Control Module >+ >+maintainers: >+ - Elaine Zhang <zhangqing@rock-chips.com> >+ - Heiko Stuebner <heiko@sntech.de> >+ - Detlev Casanova <detlev.casanova@collabora.com> >+ >+description: >+ The RK3576 clock controller generates the clock and also implements a reset >+ controller for SoC peripherals. For example it provides SCLK_UART2 and >+ PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART >+ module. >+ >+properties: >+ compatible: >+ const: rockchip,rk3576-cru >+ >+ reg: >+ maxItems: 1 >+ >+ "#clock-cells": >+ const: 1 >+ >+ "#reset-cells": >+ const: 1 >+ >+ clocks: >+ maxItems: 2 >+ >+ clock-names: >+ items: >+ - const: xin24m >+ - const: xin32k >+ >+required: >+ - compatible >+ - reg >+ - "#clock-cells" >+ - "#reset-cells" >+ >+additionalProperties: false >+ >+examples: >+ - | >+ clock-controller@27200000 { >+ compatible = "rockchip,rk3576-cru"; >+ reg = <0xfd7c0000 0x5c000>; >+ #clock-cells = <1>; >+ #reset-cells = <1>; >+ }; >diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h >new file mode 100644 >index 000000000000..ee3718452b77 >--- /dev/null >+++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h >@@ -0,0 +1,592 @@ >+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ >+/* >+* Copyright (c) 2023 Rockchip Electronics Co. Ltd. >+* Copyright (c) 2024 Collabora Ltd. >+* >+* Author: Elaine Zhang <zhangqing@rock-chips.com> >+* Author: Detlev Casanova <detlev.casanova@collabora.com> >+*/ >+ >+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H >+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H >+ >+/* cru-clocks indices */ >+ >+/* cru plls */ >+#define PLL_BPLL 0 >+#define PLL_LPLL 1 >+#define PLL_VPLL 2 >+#define PLL_AUPLL 3 >+#define PLL_CPLL 4 >+#define PLL_GPLL 5 >+#define PLL_PPLL 6 >+#define ARMCLK_L 7 >+#define ARMCLK_B 8 >+ >+/* cru clocks */ >+#define CLK_CPLL_DIV20 9 >+#define CLK_CPLL_DIV10 10 >+#define CLK_GPLL_DIV8 11 >+#define CLK_GPLL_DIV6 12 ......... >+#define SRST_OTGPHY_1 449 >+#define SRST_HDPTX_INIT 450 >+#define SRST_HDPTX_CMN 451 >+#define SRST_HDPTX_LANE 452 >+#define SRST_HDMITXHPD 453 Compared to RK3588, this should be SRST_HDMITXHDP . I think this is a typo in TRM。 >+ >+#define SRST_MPHY_INIT 454 >+#define SRST_P_MPHY_GRF 455 >+#define SRST_P_VCCIO7_IOC 456 >+ >+#define SRST_H_PMU1_BIU 457 >+#define SRST_P_PMU1_NIU 458 >+#define SRST_H_PMU_CM0_BIU 459 >+#define SRST_PMU_CM0_CORE 460 >+#define SRST_PMU_CM0_JTAG 461 >+ >+#define SRST_P_CRU_PMU1 462 >+#define SRST_P_PMU1_GRF 463 >+#define SRST_P_PMU1_IOC 464 >+#define SRST_P_PMU1WDT 465 >+#define SRST_T_PMU1WDT 466 >+#define SRST_P_PMUTIMER 467 >+#define SRST_PMUTIMER0 468 >+#define SRST_PMUTIMER1 469 >+#define SRST_P_PMU1PWM 470 >+#define SRST_PMU1PWM 471 >+ >+#define SRST_P_I2C0 472 >+#define SRST_I2C0 473 >+#define SRST_S_UART1 474 >+#define SRST_P_UART1 475 >+#define SRST_PDM0 476 >+#define SRST_H_PDM0 477 >+ >+#define SRST_M_PDM0 478 >+#define SRST_H_VAD 479 >+ >+#define SRST_P_PMU0GRF 480 >+#define SRST_P_PMU0IOC 481 >+#define SRST_P_GPIO0 482 >+#define SRST_DB_GPIO0 483 >+ >+#endif >-- >2.46.0 > > >_______________________________________________ >Linux-rockchip mailing list >Linux-rockchip@lists.infradead.org >http://lists.infradead.org/mailman/listinfo/linux-rockchip ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova 2024-08-26 11:04 ` Andy Yan @ 2024-08-26 14:00 ` Rob Herring (Arm) 1 sibling, 0 replies; 8+ messages in thread From: Rob Herring (Arm) @ 2024-08-26 14:00 UTC (permalink / raw) To: Detlev Casanova Cc: Philipp Zabel, Conor Dooley, devicetree, Sugar Zhang, Michael Turquette, Elaine Zhang, Heiko Stuebner, linux-arm-kernel, linux-rockchip, kernel, Krzysztof Kozlowski, linux-clk, linux-kernel, Stephen Boyd On Thu, 22 Aug 2024 15:49:32 -0400, Detlev Casanova wrote: > Add clock and reset ID defines for rk3576. > > Compared to the downstream bindings written by Elaine, this uses > continous gapless IDs starting at 0. Thus all numbers are > different between downstream and upstream, but names are kept > exactly the same. > > Also add documentation for the rk3576 CRU core. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > --- > .../bindings/clock/rockchip,rk3576-cru.yaml | 56 ++ > .../dt-bindings/clock/rockchip,rk3576-cru.h | 592 ++++++++++++++++++ > .../dt-bindings/reset/rockchip,rk3576-cru.h | 564 +++++++++++++++++ > 3 files changed, 1212 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml > create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h > create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h > Reviewed-by: Rob Herring (Arm) <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr 2024-08-22 19:49 [PATCH v6 0/3] Add CRU support for rk3576 SoC Detlev Casanova 2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova @ 2024-08-22 19:49 ` Detlev Casanova 2024-08-23 5:15 ` Dragan Simic 2024-08-22 19:49 ` [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 Detlev Casanova 2 siblings, 1 reply; 8+ messages in thread From: Detlev Casanova @ 2024-08-22 19:49 UTC (permalink / raw) To: linux-kernel Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, Detlev Casanova, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel From: Elaine Zhang <zhangqing@rock-chips.com> That PLL type is similar to the other rk3588 pll types but the actual rate is twice the configured rate. Therefore, the returned calculated rate must be multiplied by two. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> (cherry picked from commit c99648df60d3763723de9e443b862da44e8872fe) Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> --- drivers/clk/rockchip/clk-pll.c | 6 +++++- drivers/clk/rockchip/clk.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c index 606ce5458f54..fe76756e592e 100644 --- a/drivers/clk/rockchip/clk-pll.c +++ b/drivers/clk/rockchip/clk-pll.c @@ -914,7 +914,10 @@ static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned } rate64 = rate64 >> cur.s; - return (unsigned long)rate64; + if (pll->type == pll_rk3588_ddr) + return (unsigned long)rate64 * 2; + else + return (unsigned long)rate64; } static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll, @@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, break; case pll_rk3588: case pll_rk3588_core: + case pll_rk3588_ddr: if (!pll->rate_table) init.ops = &rockchip_rk3588_pll_clk_norate_ops; else diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index fd3b476dedda..40fc0e4703c1 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -287,6 +287,7 @@ enum rockchip_pll_type { pll_rk3399, pll_rk3588, pll_rk3588_core, + pll_rk3588_ddr, }; #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ -- 2.46.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr 2024-08-22 19:49 ` [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr Detlev Casanova @ 2024-08-23 5:15 ` Dragan Simic 0 siblings, 0 replies; 8+ messages in thread From: Dragan Simic @ 2024-08-23 5:15 UTC (permalink / raw) To: Detlev Casanova Cc: linux-kernel, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel Hello Detlev, On 2024-08-22 21:49, Detlev Casanova wrote: > From: Elaine Zhang <zhangqing@rock-chips.com> > > That PLL type is similar to the other rk3588 pll types but the actual > rate is twice the configured rate. > Therefore, the returned calculated rate must be multiplied by two. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > (cherry picked from commit c99648df60d3763723de9e443b862da44e8872fe) > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Thanks for the patch. I had a rather detailed look at the patch, while focusing on having no regressions introduced, and I found none. So, please feel free to include: Acked-by: Dragan Simic <dsimic@manjaro.org> > --- > drivers/clk/rockchip/clk-pll.c | 6 +++++- > drivers/clk/rockchip/clk.h | 1 + > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/rockchip/clk-pll.c > b/drivers/clk/rockchip/clk-pll.c > index 606ce5458f54..fe76756e592e 100644 > --- a/drivers/clk/rockchip/clk-pll.c > +++ b/drivers/clk/rockchip/clk-pll.c > @@ -914,7 +914,10 @@ static unsigned long > rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned > } > rate64 = rate64 >> cur.s; > > - return (unsigned long)rate64; > + if (pll->type == pll_rk3588_ddr) > + return (unsigned long)rate64 * 2; > + else > + return (unsigned long)rate64; > } > > static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll > *pll, > @@ -1167,6 +1170,7 @@ struct clk *rockchip_clk_register_pll(struct > rockchip_clk_provider *ctx, > break; > case pll_rk3588: > case pll_rk3588_core: > + case pll_rk3588_ddr: > if (!pll->rate_table) > init.ops = &rockchip_rk3588_pll_clk_norate_ops; > else > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index fd3b476dedda..40fc0e4703c1 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -287,6 +287,7 @@ enum rockchip_pll_type { > pll_rk3399, > pll_rk3588, > pll_rk3588_core, > + pll_rk3588_ddr, > }; > > #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1, \ ^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 2024-08-22 19:49 [PATCH v6 0/3] Add CRU support for rk3576 SoC Detlev Casanova 2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova 2024-08-22 19:49 ` [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr Detlev Casanova @ 2024-08-22 19:49 ` Detlev Casanova 2024-08-23 5:16 ` Dragan Simic 2 siblings, 1 reply; 8+ messages in thread From: Detlev Casanova @ 2024-08-22 19:49 UTC (permalink / raw) To: linux-kernel Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, Detlev Casanova, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel, Finley Xiao, YouMin Chen, Liang Chen, Sugar Zhang, Shawn Lin From: Elaine Zhang <zhangqing@rock-chips.com> Add the clock and reset tree definitions for the new RK3576 SoC. As opposed to the other rockchip CRU drivers, the GRF node is looked up via compatible instead of a phandle, which simplifies the device tree bindings. Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> Tested-by: Shawn Lin <shawn.lin@rock-chips.com> --- drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-rk3576.c | 1829 +++++++++++++++++++++++++++++ drivers/clk/rockchip/clk.h | 53 + drivers/clk/rockchip/rst-rk3576.c | 652 ++++++++++ 5 files changed, 2542 insertions(+) create mode 100644 drivers/clk/rockchip/clk-rk3576.c create mode 100644 drivers/clk/rockchip/rst-rk3576.c diff --git a/drivers/clk/rockchip/Kconfig b/drivers/clk/rockchip/Kconfig index 9aad86925cd2..f8eb16f170d4 100644 --- a/drivers/clk/rockchip/Kconfig +++ b/drivers/clk/rockchip/Kconfig @@ -100,6 +100,13 @@ config CLK_RK3568 help Build the driver for RK3568 Clock Driver. +config CLK_RK3576 + tristate "Rockchip RK3576 clock controller support" + depends on ARM64 || COMPILE_TEST + default y + help + Build the driver for RK3576 Clock Driver. + config CLK_RK3588 bool "Rockchip RK3588 clock controller support" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 36894f6a7022..af2ade54a7ef 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o +obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o diff --git a/drivers/clk/rockchip/clk-rk3576.c b/drivers/clk/rockchip/clk-rk3576.c new file mode 100644 index 000000000000..a002b119cc6b --- /dev/null +++ b/drivers/clk/rockchip/clk-rk3576.c @@ -0,0 +1,1829 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. + * Author: Elaine Zhang <zhangqing@rock-chips.com> + */ + +#include <linux/clk-provider.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_address.h> +#include <linux/syscore_ops.h> +#include <linux/mfd/syscon.h> +#include <dt-bindings/clock/rockchip,rk3576-cru.h> +#include "clk.h" + +#define RK3576_GRF_SOC_STATUS0 0x600 +#define RK3576_PMU0_GRF_OSC_CON6 0x18 + +enum rk3576_plls { + bpll, lpll, vpll, aupll, cpll, gpll, ppll, +}; + +static struct rockchip_pll_rate_table rk3576_pll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_rate_table rk3576_ppll_rates[] = { + /* _mhz, _p, _m, _s, _k */ + RK3588_PLL_RATE(1300000000, 3, 325, 2, 0), + { /* sentinel */ }, +}; + +#define RK3576_ACLK_M_BIGCORE_DIV_MASK 0x1f +#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0 +#define RK3576_ACLK_M_LITCORE_DIV_MASK 0x1f +#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8 +#define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0x1f +#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0 +#define RK3576_ACLK_CCI_DIV_MASK 0x1f +#define RK3576_ACLK_CCI_DIV_SHIFT 7 +#define RK3576_ACLK_CCI_MUX_MASK 0x3 +#define RK3576_ACLK_CCI_MUX_SHIFT 12 + +#define RK3576_BIGCORE_CLKSEL2(_amcore) \ +{ \ + .reg = RK3576_BIGCORE_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \ + RK3576_ACLK_M_BIGCORE_DIV_SHIFT), \ +} + +#define RK3576_LITCORE_CLKSEL1(_amcore) \ +{ \ + .reg = RK3576_LITCORE_CLKSEL_CON(1), \ + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \ + RK3576_ACLK_M_LITCORE_DIV_SHIFT), \ +} + +#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \ +{ \ + .reg = RK3576_LITCORE_CLKSEL_CON(2), \ + .val = HIWORD_UPDATE(_pclkdbg - 1, RK3576_PCLK_DBG_LITCORE_DIV_MASK, \ + RK3576_PCLK_DBG_LITCORE_DIV_SHIFT), \ +} + +#define RK3576_CCI_CLKSEL4(_ccisel, _div) \ +{ \ + .reg = RK3576_CCI_CLKSEL_CON(4), \ + .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \ + RK3576_ACLK_CCI_MUX_SHIFT) | \ + HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \ + RK3576_ACLK_CCI_DIV_SHIFT), \ +} + +#define RK3576_CPUBCLK_RATE(_prate, _amcore) \ +{ \ + .prate = _prate##U, \ + .divs = { \ + RK3576_BIGCORE_CLKSEL2(_amcore), \ + }, \ +} + +#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \ +{ \ + .prate = _prate##U, \ + .divs = { \ + RK3576_LITCORE_CLKSEL1(_amcore), \ + RK3576_LITCORE_CLKSEL2(_pclkdbg), \ + }, \ + .pre_muxs = { \ + RK3576_CCI_CLKSEL4(2, 2), \ + }, \ + .post_muxs = { \ + RK3576_CCI_CLKSEL4(_ccisel, 2), \ + }, \ +} + +static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] __initdata = { + RK3576_CPUBCLK_RATE(2496000000, 2), + RK3576_CPUBCLK_RATE(2400000000, 2), + RK3576_CPUBCLK_RATE(2304000000, 2), + RK3576_CPUBCLK_RATE(2208000000, 2), + RK3576_CPUBCLK_RATE(2184000000, 2), + RK3576_CPUBCLK_RATE(2088000000, 2), + RK3576_CPUBCLK_RATE(2040000000, 2), + RK3576_CPUBCLK_RATE(2016000000, 2), + RK3576_CPUBCLK_RATE(1992000000, 2), + RK3576_CPUBCLK_RATE(1896000000, 2), + RK3576_CPUBCLK_RATE(1800000000, 2), + RK3576_CPUBCLK_RATE(1704000000, 2), + RK3576_CPUBCLK_RATE(1608000000, 2), + RK3576_CPUBCLK_RATE(1584000000, 2), + RK3576_CPUBCLK_RATE(1560000000, 2), + RK3576_CPUBCLK_RATE(1536000000, 2), + RK3576_CPUBCLK_RATE(1512000000, 2), + RK3576_CPUBCLK_RATE(1488000000, 2), + RK3576_CPUBCLK_RATE(1464000000, 2), + RK3576_CPUBCLK_RATE(1440000000, 2), + RK3576_CPUBCLK_RATE(1416000000, 2), + RK3576_CPUBCLK_RATE(1392000000, 2), + RK3576_CPUBCLK_RATE(1368000000, 2), + RK3576_CPUBCLK_RATE(1344000000, 2), + RK3576_CPUBCLK_RATE(1320000000, 2), + RK3576_CPUBCLK_RATE(1296000000, 2), + RK3576_CPUBCLK_RATE(1272000000, 2), + RK3576_CPUBCLK_RATE(1248000000, 2), + RK3576_CPUBCLK_RATE(1224000000, 2), + RK3576_CPUBCLK_RATE(1200000000, 2), + RK3576_CPUBCLK_RATE(1104000000, 2), + RK3576_CPUBCLK_RATE(1008000000, 2), + RK3576_CPUBCLK_RATE(912000000, 2), + RK3576_CPUBCLK_RATE(816000000, 2), + RK3576_CPUBCLK_RATE(696000000, 2), + RK3576_CPUBCLK_RATE(600000000, 2), + RK3576_CPUBCLK_RATE(408000000, 2), + RK3576_CPUBCLK_RATE(312000000, 2), + RK3576_CPUBCLK_RATE(216000000, 2), + RK3576_CPUBCLK_RATE(96000000, 2), +}; + +static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = { + .core_reg[0] = RK3576_BIGCORE_CLKSEL_CON(1), + .div_core_shift[0] = 7, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 12, + .mux_core_mask = 0x3, +}; + +static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] __initdata = { + RK3576_CPULCLK_RATE(2400000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2304000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2208000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2184000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2088000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2040000000, 2, 6, 3), + RK3576_CPULCLK_RATE(2016000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1992000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1896000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1800000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1704000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1608000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1584000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1560000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1536000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1512000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1488000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1464000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1440000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1416000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1392000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1368000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1344000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1320000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1296000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1272000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1248000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1224000000, 2, 6, 3), + RK3576_CPULCLK_RATE(1200000000, 2, 6, 2), + RK3576_CPULCLK_RATE(1104000000, 2, 6, 2), + RK3576_CPULCLK_RATE(1008000000, 2, 6, 2), + RK3576_CPULCLK_RATE(912000000, 2, 6, 2), + RK3576_CPULCLK_RATE(816000000, 2, 6, 2), + RK3576_CPULCLK_RATE(696000000, 2, 6, 2), + RK3576_CPULCLK_RATE(600000000, 2, 6, 2), + RK3576_CPULCLK_RATE(408000000, 2, 6, 2), + RK3576_CPULCLK_RATE(312000000, 2, 6, 2), + RK3576_CPULCLK_RATE(216000000, 2, 6, 2), + RK3576_CPULCLK_RATE(96000000, 2, 6, 2), +}; + +static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = { + .core_reg[0] = RK3576_LITCORE_CLKSEL_CON(0), + .div_core_shift[0] = 7, + .div_core_mask[0] = 0x1f, + .num_cores = 1, + .mux_core_alt = 1, + .mux_core_main = 0, + .mux_core_shift = 12, + .mux_core_mask = 0x3, +}; + +#define MFLAGS CLK_MUX_HIWORD_MASK +#define DFLAGS CLK_DIVIDER_HIWORD_MASK +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) + +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; +PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" }; +PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" }; +PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" }; +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; +PNAME(cpll_24m_p) = { "cpll", "xin24m" }; +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; +PNAME(gpll_spll_p) = { "gpll", "spll" }; +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" }; +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; +PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" }; +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; +PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", "spll", "lpll_dummy" }; +PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" }; +PNAME(gpll_cpll_lpll_bpll_p) = { "gpll", "cpll", "lpll_dummy", "bpll_dummy" }; +PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", "bpll_dummy", "lpll_dummy" }; +PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" }; +PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", "aupll", "bpll_dummy" }; +PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", "bpll_dummy", "lpll_dummy" }; +PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", "lpll_dummy", "bpll_dummy" }; +PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy", "lpll_dummy" }; +PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", "bpll_dummy", "lpll_dummy" }; +PNAME(gpll_spll_isppvtpll_bpll_lpll_p) = { "gpll", "spll", "isp_pvtpll", "bpll_dummy", "lpll_dummy" }; +PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", "aupll", "lpll_dummy", "xin24m" }; +PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", "vpll", "bpll_dummy", "lpll_dummy" }; +PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", "bpll_dummy" }; +PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", "gpll", "lpll" }; +PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" }; +PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", + "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", "clk_audio_int_2" }; +PNAME(audio_frac_p) = { "clk_audio_frac_0", "clk_audio_frac_1", "clk_audio_frac_2", "clk_audio_frac_3" }; +PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; +PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; +PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_0" }; +PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", "lclk_asrc_src_1" }; +PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; +PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; +PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", "clk_gpll_div6", "clk_cpll_div10", "xin24m" }; +PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", "clk_cpll_div4", "clk_cpll_div10", "xin24m" }; +PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", "clk_gpll_div3", "clk_gpll_div4", "xin24m" }; +PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", "clk_spll_div4", "clk_spll_div6", "xin24m" }; +PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", "clk_spll_div12", "xin24m" }; +PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", "xin24m" }; +PNAME(mclk_sai0_8ch_p) = { "mclk_sai0_8ch_src", "sai0_mclkin", "sai1_mclkin" }; +PNAME(mclk_sai1_8ch_p) = { "mclk_sai1_8ch_src", "sai1_mclkin" }; +PNAME(mclk_sai2_2ch_p) = { "mclk_sai2_2ch_src", "sai2_mclkin", "sai1_mclkin" }; +PNAME(mclk_sai3_2ch_p) = { "mclk_sai3_2ch_src", "sai3_mclkin", "sai1_mclkin" }; +PNAME(mclk_sai4_2ch_p) = { "mclk_sai4_2ch_src", "sai4_mclkin", "sai1_mclkin" }; +PNAME(mclk_sai5_8ch_p) = { "mclk_sai5_8ch_src", "sai1_mclkin" }; +PNAME(mclk_sai6_8ch_p) = { "mclk_sai6_8ch_src", "sai1_mclkin" }; +PNAME(mclk_sai7_8ch_p) = { "mclk_sai7_8ch_src", "sai1_mclkin" }; +PNAME(mclk_sai8_8ch_p) = { "mclk_sai8_8ch_src", "sai1_mclkin" }; +PNAME(mclk_sai9_8ch_p) = { "mclk_sai9_8ch_src", "sai1_mclkin" }; +PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" }; +PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; +PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; +PNAME(clk_gmac1_ptp_ref_src_p) = { "gpll", "cpll", "gmac1_ptp_refclk_in" }; +PNAME(clk_gmac0_ptp_ref_src_p) = { "gpll", "cpll", "gmac0_ptp_refclk_in" }; +PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy", + "dclk_ebc_frac", "xin24m" }; +PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" }; +PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" }; +PNAME(dclk_vp2_p) = { "dclk_vp2_src", "clk_hdmiphy_pixel0" }; +PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", "clk_uart_frac_0", + "clk_uart_frac_1", "clk_uart_frac_2"}; +PNAME(clk_freq_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_freq"}; +PNAME(clk_counter_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", "sai2_mclkin", + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_counter"}; +PNAME(sai_sclkin_freq_p) = { "sai0_sclk_in", "sai1_sclk_in", "sai2_sclk_in", + "sai3_sclk_in", "sai4_sclk_in"}; +PNAME(clk_ref_pcie0_phy_p) = { "clk_pcie_100m_src", "clk_pcie_100m_nduty_src", + "xin24m"}; +PNAME(hclk_vi_root_p) = { "clk_gpll_div6", "clk_cpll_div10", + "aclk_vi_root_inter", "xin24m"}; +PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", "clk_ref_mphy_26m"}; +PNAME(mux_pmu200m_pmu100m_pmu50m_24m_p) = { "clk_200m_pmu_src", "clk_100m_pmu_src", + "clk_50m_pmu_src", "xin24m" }; +PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", "clk_50m_pmu_src", "xin24m" }; +PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", "xin_osc0_div" }; +PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" }; +PNAME(clk_usbphy_ref_src_p) = { "usbphy0_24m", "usbphy1_24m" }; +PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" }; +PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" }; + +static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = { + [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p, + 0, RK3576_PLL_CON(0), + RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, + 0, RK3576_LPLL_CON(16), + RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), + [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p, + 0, RK3576_PLL_CON(88), + RK3576_MODE_CON0, 4, 15, 0, rk3576_pll_rates), + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, + 0, RK3576_PLL_CON(96), + RK3576_MODE_CON0, 6, 15, 0, rk3576_pll_rates), + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3576_PLL_CON(104), + RK3576_MODE_CON0, 8, 15, 0, rk3576_pll_rates), + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3576_PLL_CON(112), + RK3576_MODE_CON0, 2, 15, 0, rk3576_pll_rates), + [ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p, + CLK_IGNORE_UNUSED, RK3576_PMU_PLL_CON(128), + RK3576_MODE_CON0, 10, 15, 0, rk3576_ppll_rates), +}; + +static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { + /* + * CRU Clock-Architecture + */ + /* fixed */ + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), + + COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", CLK_IS_CRITICAL, + RK3576_PMU_CLKSEL_CON(21), 0, + RK3576_PMU_CLKGATE_CON(7), 11, GFLAGS), + + FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12), + FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6), + FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4), + FACTOR(0, "lpll_div2", "lpll", 0, 1, 2), + FACTOR(0, "bpll_div4", "bpll", 0, 1, 4), + + /* top */ + COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 2, GFLAGS), + COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 3, GFLAGS), + COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 4, GFLAGS), + COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 5, GFLAGS), + COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(3), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 6, GFLAGS), + COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 9, GFLAGS), + COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 10, GFLAGS), + COMPOSITE(CLK_SPLL_DIV1, "clk_spll_div1", gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(6), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(8), 7, 2, MFLAGS, + RK3576_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_aupll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(1), 3, GFLAGS), + COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(1), 6, GFLAGS), + COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(10), 11, 3, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(1), 7, GFLAGS), + COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(19), 2, 2, MFLAGS, + RK3576_CLKGATE_CON(1), 14, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0VOP_CHANNEL, "hclk_vo0vop_channel", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(19), 6, 2, MFLAGS, + RK3576_CLKGATE_CON(2), 0, GFLAGS), + COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS, + RK3576_CLKGATE_CON(2), 1, GFLAGS), + MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(13), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", "clk_audio_frac_0_src", 0, + RK3576_CLKSEL_CON(12), 0, + RK3576_CLKGATE_CON(1), 10, GFLAGS), + MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(15), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", "clk_audio_frac_1_src", 0, + RK3576_CLKSEL_CON(14), 0, + RK3576_CLKGATE_CON(1), 11, GFLAGS), + MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(17), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", "clk_audio_frac_2_src", 0, + RK3576_CLKSEL_CON(16), 0, + RK3576_CLKGATE_CON(1), 12, GFLAGS), + MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(19), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", "clk_audio_frac_3_src", 0, + RK3576_CLKSEL_CON(18), 0, + RK3576_CLKGATE_CON(1), 13, GFLAGS), + MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(22), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", "clk_uart_frac_0_src", 0, + RK3576_CLKSEL_CON(21), 0, + RK3576_CLKGATE_CON(2), 5, GFLAGS), + MUX(0, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(24), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", "clk_uart_frac_1_src", 0, + RK3576_CLKSEL_CON(23), 0, + RK3576_CLKGATE_CON(2), 6, GFLAGS), + MUX(0, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(26), 0, 2, MFLAGS), + COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", "clk_uart_frac_2_src", 0, + RK3576_CLKSEL_CON(25), 0, + RK3576_CLKGATE_CON(2), 7, GFLAGS), + COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_p, 0, + RK3576_CLKSEL_CON(27), 13, 3, MFLAGS, 5, 8, DFLAGS, + RK3576_CLKGATE_CON(2), 13, GFLAGS), + COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "gpll", 0, + RK3576_CLKSEL_CON(28), 0, 5, DFLAGS, + RK3576_CLKGATE_CON(2), 14, GFLAGS), + COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "cpll", 0, + RK3576_CLKSEL_CON(28), 5, 5, DFLAGS, + RK3576_CLKGATE_CON(2), 15, GFLAGS), + COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0, + RK3576_CLKSEL_CON(28), 10, 5, DFLAGS, + RK3576_CLKGATE_CON(3), 0, GFLAGS), + COMPOSITE(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(29), 9, 3, MFLAGS, 0, 9, DFLAGS, + RK3576_CLKGATE_CON(3), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0, + RK3576_CLKSEL_CON(30), 10, 5, DFLAGS, + RK3576_CLKGATE_CON(3), 6, GFLAGS), + COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0, + RK3576_CLKSEL_CON(31), 0, 5, DFLAGS, + RK3576_CLKGATE_CON(3), 7, GFLAGS), + COMPOSITE(LCLK_ASRC_SRC_0, "lclk_asrc_src_0", audio_frac_p, 0, + RK3576_CLKSEL_CON(31), 10, 2, MFLAGS, 5, 5, DFLAGS, + RK3576_CLKGATE_CON(3), 10, GFLAGS), + COMPOSITE(LCLK_ASRC_SRC_1, "lclk_asrc_src_1", audio_frac_p, 0, + RK3576_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(3), 11, GFLAGS), + COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, + RK3576_CLKSEL_CON(33), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(4), 1, GFLAGS), + COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, + RK3576_CLKSEL_CON(34), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(4), 2, GFLAGS), + COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", gpll_cpll_spll_aupll_lpll_24m_p, 0, + RK3576_CLKSEL_CON(35), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(4), 3, GFLAGS), + COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3576_CLKGATE_CON(5), 10, GFLAGS), + COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(36), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3576_CLKGATE_CON(5), 11, GFLAGS), + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, + RK3576_CLKSEL_CON(37), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(5), 12, GFLAGS), + GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0, + RK3576_CLKGATE_CON(5), 13, GFLAGS), + GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0, + RK3576_CLKGATE_CON(5), 14, GFLAGS), + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, + RK3576_CLKGATE_CON(5), 15, GFLAGS), + COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", mux_24m_spll_gpll_cpll_p, 0, + RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(6), 3, GFLAGS), + COMPOSITE(CLK_MIPI_CAMERAOUT_M1, "clk_mipi_cameraout_m1", mux_24m_spll_gpll_cpll_p, 0, + RK3576_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(6), 4, GFLAGS), + COMPOSITE(CLK_MIPI_CAMERAOUT_M2, "clk_mipi_cameraout_m2", mux_24m_spll_gpll_cpll_p, 0, + RK3576_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(6), 5, GFLAGS), + COMPOSITE(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(41), 7, 3, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(6), 8, GFLAGS), + + /* bus */ + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(55), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(11), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(55), 2, 2, MFLAGS, + RK3576_CLKGATE_CON(11), 1, GFLAGS), + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(55), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3576_CLKGATE_CON(11), 2, GFLAGS), + GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0, + RK3576_CLKGATE_CON(11), 6, GFLAGS), + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(56), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(11), 7, GFLAGS), + GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0, + RK3576_CLKGATE_CON(11), 8, GFLAGS), + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(56), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(11), 9, GFLAGS), + GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(11), 15, GFLAGS), + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 0, GFLAGS), + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 1, GFLAGS), + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 2, GFLAGS), + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 3, GFLAGS), + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 4, GFLAGS), + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 5, GFLAGS), + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 6, GFLAGS), + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 7, GFLAGS), + GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 8, GFLAGS), + GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(12), 9, GFLAGS), + GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0, + RK3576_CLKGATE_CON(12), 10, GFLAGS), + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(12), 11, GFLAGS), + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(12), 12, GFLAGS), + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 2, 2, MFLAGS, + RK3576_CLKGATE_CON(12), 13, GFLAGS), + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 4, 2, MFLAGS, + RK3576_CLKGATE_CON(12), 14, GFLAGS), + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 6, 2, MFLAGS, + RK3576_CLKGATE_CON(12), 15, GFLAGS), + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(13), 0, GFLAGS), + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(13), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 12, 2, MFLAGS, + RK3576_CLKGATE_CON(13), 2, GFLAGS), + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(57), 14, 2, MFLAGS, + RK3576_CLKGATE_CON(13), 3, GFLAGS), + COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(58), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(13), 4, GFLAGS), + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 6, GFLAGS), + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, + RK3576_CLKSEL_CON(58), 12, 1, MFLAGS, 4, 8, DFLAGS, + RK3576_CLKGATE_CON(13), 7, GFLAGS), + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, + RK3576_CLKSEL_CON(59), 0, 8, DFLAGS, + RK3576_CLKGATE_CON(13), 9, GFLAGS), + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 10, GFLAGS), + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 11, GFLAGS), + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 12, GFLAGS), + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 13, GFLAGS), + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 14, GFLAGS), + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(13), 15, GFLAGS), + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(14), 0, GFLAGS), + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(14), 1, GFLAGS), + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(14), 2, GFLAGS), + GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(14), 3, GFLAGS), + GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(14), 4, GFLAGS), + COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0, + RK3576_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(14), 5, GFLAGS), + COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0, + RK3576_CLKSEL_CON(61), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(14), 6, GFLAGS), + COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0, + RK3576_CLKSEL_CON(62), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(14), 9, GFLAGS), + COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0, + RK3576_CLKSEL_CON(63), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(14), 12, GFLAGS), + COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0, + RK3576_CLKSEL_CON(64), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(14), 15, GFLAGS), + COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0, + RK3576_CLKSEL_CON(65), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 2, GFLAGS), + COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0, + RK3576_CLKSEL_CON(66), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 5, GFLAGS), + COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0, + RK3576_CLKSEL_CON(67), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 8, GFLAGS), + COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_p, 0, + RK3576_CLKSEL_CON(68), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 9, GFLAGS), + COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_p, 0, + RK3576_CLKSEL_CON(69), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 10, GFLAGS), + COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_p, 0, + RK3576_CLKSEL_CON(70), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(15), 11, GFLAGS), + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(15), 13, GFLAGS), + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(15), 14, GFLAGS), + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(15), 15, GFLAGS), + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(16), 0, GFLAGS), + GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(16), 1, GFLAGS), + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(70), 13, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 2, GFLAGS), + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(71), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 3, GFLAGS), + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(71), 2, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 4, GFLAGS), + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(71), 4, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 5, GFLAGS), + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(71), 6, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 6, GFLAGS), + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(16), 7, GFLAGS), + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, + RK3576_CLKGATE_CON(16), 8, GFLAGS), + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(16), 10, GFLAGS), + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(71), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(16), 11, GFLAGS), + GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, + RK3576_CLKGATE_CON(16), 13, GFLAGS), + GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0, + RK3576_CLKGATE_CON(16), 15, GFLAGS), + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(17), 3, GFLAGS), + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(17), 4, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, 0, + RK3576_CLKSEL_CON(71), 14, 1, MFLAGS, + RK3576_CLKGATE_CON(17), 5, GFLAGS), + GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 6, GFLAGS), + GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 7, GFLAGS), + GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 8, GFLAGS), + GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 9, GFLAGS), + GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 10, GFLAGS), + GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0, + RK3576_CLKGATE_CON(17), 11, GFLAGS), + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(17), 13, GFLAGS), + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(17), 15, GFLAGS), + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, + RK3576_CLKGATE_CON(18), 0, GFLAGS), + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(18), 1, GFLAGS), + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, + RK3576_CLKGATE_CON(18), 2, GFLAGS), + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(18), 3, GFLAGS), + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, + RK3576_CLKGATE_CON(18), 4, GFLAGS), + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(18), 5, GFLAGS), + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, + RK3576_CLKGATE_CON(18), 6, GFLAGS), + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, + RK3576_CLKGATE_CON(18), 7, GFLAGS), + GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(18), 8, GFLAGS), + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, + RK3576_CLKSEL_CON(72), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(18), 9, GFLAGS), + COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, 0, + RK3576_CLKSEL_CON(72), 6, 1, MFLAGS, + RK3576_CLKGATE_CON(18), 10, GFLAGS), + GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0, + RK3576_CLKGATE_CON(18), 11, GFLAGS), + COMPOSITE(CLK_TIMER7, "clk_timer7", mux_100m_24m_lclk0_p, 0, + RK3576_CLKSEL_CON(72), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(18), 12, GFLAGS), + COMPOSITE(CLK_TIMER8, "clk_timer8", mux_100m_24m_lclk1_p, 0, + RK3576_CLKSEL_CON(73), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(18), 13, GFLAGS), + GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0, + RK3576_CLKGATE_CON(18), 14, GFLAGS), + GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0, + RK3576_CLKGATE_CON(18), 15, GFLAGS), + GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0, + RK3576_CLKGATE_CON(19), 0, GFLAGS), + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 1, GFLAGS), + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 2, GFLAGS), + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 3, GFLAGS), + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 4, GFLAGS), + GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 7, GFLAGS), + GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0, + RK3576_CLKGATE_CON(19), 9, GFLAGS), + COMPOSITE_NODIV(HCLK_BUS_CM0_ROOT, "hclk_bus_cm0_root", mux_400m_200m_100m_24m_p, 0, + RK3576_CLKSEL_CON(73), 13, 2, MFLAGS, + RK3576_CLKGATE_CON(19), 10, GFLAGS), + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0, + RK3576_CLKGATE_CON(19), 12, GFLAGS), + COMPOSITE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", mux_24m_32k_p, 0, + RK3576_CLKSEL_CON(74), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(19), 14, GFLAGS), + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(19), 15, GFLAGS), + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(20), 4, GFLAGS), + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(74), 6, 2, MFLAGS, + RK3576_CLKGATE_CON(20), 5, GFLAGS), + GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, + RK3576_CLKGATE_CON(20), 7, GFLAGS), + GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0, + RK3576_CLKGATE_CON(20), 6, GFLAGS), + COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0, + RK3576_CLKSEL_CON(74), 8, 3, MFLAGS, + RK3576_CLKGATE_CON(20), 8, GFLAGS), + COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", clk_counter_pwm1_p, 0, + RK3576_CLKSEL_CON(74), 11, 3, MFLAGS, + RK3576_CLKGATE_CON(20), 9, GFLAGS), + COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", sai_sclkin_freq_p, 0, + RK3576_CLKSEL_CON(75), 0, 3, MFLAGS, + RK3576_CLKGATE_CON(20), 10, GFLAGS), + COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", sai_sclkin_freq_p, 0, + RK3576_CLKSEL_CON(75), 3, 3, MFLAGS, + RK3576_CLKGATE_CON(20), 11, GFLAGS), + COMPOSITE(CLK_I3C0, "clk_i3c0", gpll_cpll_aupll_spll_p, 0, + RK3576_CLKSEL_CON(78), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(20), 12, GFLAGS), + COMPOSITE(CLK_I3C1, "clk_i3c1", gpll_cpll_aupll_spll_p, 0, + RK3576_CLKSEL_CON(78), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(20), 13, GFLAGS), + GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0, + RK3576_CLKGATE_CON(40), 2, GFLAGS), + + /* cci */ + COMPOSITE(PCLK_CCI_ROOT, "pclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CCI_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CCI_CLKGATE_CON(1), 10, GFLAGS), + COMPOSITE(ACLK_CCI_ROOT, "aclk_cci_root", mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CCI_CLKSEL_CON(4), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CCI_CLKGATE_CON(1), 11, GFLAGS), + + /* center */ + COMPOSITE_DIV_OFFSET(ACLK_CENTER_ROOT, "aclk_center_root", gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(168), 5, 3, MFLAGS, + RK3576_CLKSEL_CON(167), 9, 5, DFLAGS, + RK3576_CLKGATE_CON(72), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(168), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(72), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(168), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(72), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(168), 12, 2, MFLAGS, + RK3576_CLKGATE_CON(72), 3, GFLAGS), + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IGNORE_UNUSED, + RK3576_CLKGATE_CON(72), 5, GFLAGS), + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IGNORE_UNUSED, + RK3576_CLKGATE_CON(72), 6, GFLAGS), + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3576_CLKGATE_CON(72), 10, GFLAGS), + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IGNORE_UNUSED, + RK3576_CLKGATE_CON(72), 11, GFLAGS), + + /* ddr */ + COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(21), 0, GFLAGS), + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", CLK_IGNORE_UNUSED, + RK3576_CLKGATE_CON(21), 1, GFLAGS), + COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, CLK_IGNORE_UNUSED, + RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(22), 11, GFLAGS), + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(22), 15, GFLAGS), + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_100m_24m_p, 0, + RK3576_CLKSEL_CON(77), 6, 1, MFLAGS, + RK3576_CLKGATE_CON(23), 3, GFLAGS), + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, + RK3576_CLKGATE_CON(23), 4, GFLAGS), + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, + RK3576_CLKGATE_CON(23), 5, GFLAGS), + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, + RK3576_CLKGATE_CON(23), 6, GFLAGS), + GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0, + RK3576_CLKGATE_CON(23), 7, GFLAGS), + GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0, + RK3576_CLKGATE_CON(23), 8, GFLAGS), + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, 0, + RK3576_CLKSEL_CON(77), 12, 1, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(23), 10, GFLAGS), + + /* gpu */ + COMPOSITE(CLK_GPU_SRC_PRE, "clk_gpu_src_pre", gpll_cpll_aupll_spll_lpll_p, 0, + RK3576_CLKSEL_CON(165), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(69), 1, GFLAGS), + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0, + RK3576_CLKGATE_CON(69), 3, GFLAGS), + COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(166), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(69), 8, GFLAGS), + + /* npu */ + COMPOSITE_NODIV(HCLK_RKNN_ROOT, "hclk_rknn_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(86), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(31), 4, GFLAGS), + COMPOSITE(CLK_RKNN_DSU0, "clk_rknn_dsu0", gpll_cpll_aupll_spll_p, 0, + RK3576_CLKSEL_CON(86), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(31), 5, GFLAGS), + GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0, + RK3576_CLKGATE_CON(28), 9, GFLAGS), + GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0, + RK3576_CLKGATE_CON(29), 0, GFLAGS), + COMPOSITE_NODIV(PCLK_NPUTOP_ROOT, "pclk_nputop_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(87), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(31), 8, GFLAGS), + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0, + RK3576_CLKGATE_CON(31), 10, GFLAGS), + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_100m_24m_p, 0, + RK3576_CLKSEL_CON(87), 2, 1, MFLAGS, + RK3576_CLKGATE_CON(31), 11, GFLAGS), + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, + RK3576_CLKGATE_CON(31), 12, GFLAGS), + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, + RK3576_CLKGATE_CON(31), 13, GFLAGS), + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0, + RK3576_CLKGATE_CON(31), 14, GFLAGS), + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, + RK3576_CLKGATE_CON(31), 15, GFLAGS), + GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0, + RK3576_CLKGATE_CON(32), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0, + RK3576_CLKSEL_CON(87), 3, 2, MFLAGS, + RK3576_CLKGATE_CON(32), 5, GFLAGS), + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, + RK3576_CLKGATE_CON(32), 7, GFLAGS), + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, + RK3576_CLKSEL_CON(87), 10, 1, MFLAGS, 5, 5, DFLAGS, + RK3576_CLKGATE_CON(32), 9, GFLAGS), + GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0, + RK3576_CLKGATE_CON(32), 12, GFLAGS), + + /* nvm */ + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(88), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(33), 0, GFLAGS), + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(88), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(33), 1, GFLAGS), + COMPOSITE(SCLK_FSPI_X2, "sclk_fspi_x2", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(89), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3576_CLKGATE_CON(33), 6, GFLAGS), + GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0, + RK3576_CLKGATE_CON(33), 7, GFLAGS), + COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(89), 14, 2, MFLAGS, 8, 6, DFLAGS, + RK3576_CLKGATE_CON(33), 8, GFLAGS), + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0, + RK3576_CLKGATE_CON(33), 9, GFLAGS), + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, + RK3576_CLKGATE_CON(33), 10, GFLAGS), + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(90), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(33), 11, GFLAGS), + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, + RK3576_CLKGATE_CON(33), 12, GFLAGS), + + /* usb */ + COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(115), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(47), 0, GFLAGS), + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(115), 11, 1, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(47), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_USB_ROOT, "pclk_usb_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(115), 12, 2, MFLAGS, + RK3576_CLKGATE_CON(47), 2, GFLAGS), + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0, + RK3576_CLKGATE_CON(47), 5, GFLAGS), + GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0, + RK3576_CLKGATE_CON(47), 6, GFLAGS), + GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0, + RK3576_CLKGATE_CON(47), 7, GFLAGS), + GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0, + RK3576_CLKGATE_CON(47), 12, GFLAGS), + GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0, + RK3576_CLKGATE_CON(47), 13, GFLAGS), + GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0, + RK3576_CLKGATE_CON(47), 15, GFLAGS), + + /* vdec */ + COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(110), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(45), 0, GFLAGS), + COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", gpll_cpll_aupll_spll_p, 0, + RK3576_CLKSEL_CON(110), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(45), 1, GFLAGS), + COMPOSITE(ACLK_RKVDEC_ROOT_BAK, "aclk_rkvdec_root_bak", cpll_vpll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(110), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3576_CLKGATE_CON(45), 2, GFLAGS), + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, + RK3576_CLKGATE_CON(45), 3, GFLAGS), + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", gpll_cpll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(111), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(45), 8, GFLAGS), + GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0, + RK3576_CLKGATE_CON(45), 9, GFLAGS), + + /* venc */ + COMPOSITE_NODIV(HCLK_VEPU0_ROOT, "hclk_vepu0_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(124), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(51), 0, GFLAGS), + COMPOSITE(ACLK_VEPU0_ROOT, "aclk_vepu0_root", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(51), 1, GFLAGS), + COMPOSITE(CLK_VEPU0_CORE, "clk_vepu0_core", gpll_cpll_spll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(124), 13, 3, MFLAGS, 8, 5, DFLAGS, + RK3576_CLKGATE_CON(51), 6, GFLAGS), + GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0, + RK3576_CLKGATE_CON(51), 4, GFLAGS), + GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0, + RK3576_CLKGATE_CON(51), 5, GFLAGS), + + /* vi */ + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(128), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(53), 0, GFLAGS), + COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", "aclk_vi_root", 0, + RK3576_CLKSEL_CON(130), 10, 3, DFLAGS, + RK3576_CLKGATE_CON(54), 13, GFLAGS), + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(128), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(53), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(128), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(53), 2, GFLAGS), + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(129), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(53), 6, GFLAGS), + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, + RK3576_CLKGATE_CON(53), 7, GFLAGS), + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, + RK3576_CLKGATE_CON(53), 8, GFLAGS), + COMPOSITE(CLK_ISP_CORE, "clk_isp_core", gpll_spll_isppvtpll_bpll_lpll_p, 0, + RK3576_CLKSEL_CON(129), 11, 3, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(53), 9, GFLAGS), + GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0, + RK3576_CLKGATE_CON(53), 10, GFLAGS), + GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0, + RK3576_CLKGATE_CON(53), 11, GFLAGS), + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, + RK3576_CLKGATE_CON(53), 12, GFLAGS), + GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, + RK3576_CLKGATE_CON(53), 13, GFLAGS), + GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, + RK3576_CLKGATE_CON(53), 15, GFLAGS), + GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 0, GFLAGS), + GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0, + RK3576_CLKGATE_CON(54), 1, GFLAGS), + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 4, GFLAGS), + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 5, GFLAGS), + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 6, GFLAGS), + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 7, GFLAGS), + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, + RK3576_CLKGATE_CON(54), 8, GFLAGS), + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0, + RK3576_CLKSEL_CON(130), 7, 2, MFLAGS, + RK3576_CLKGATE_CON(54), 10, GFLAGS), + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, + RK3576_CLKGATE_CON(54), 11, GFLAGS), + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(144), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(61), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(144), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(61), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(144), 12, 2, MFLAGS, + RK3576_CLKGATE_CON(61), 3, GFLAGS), + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, + RK3576_CLKGATE_CON(61), 8, GFLAGS), + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, + RK3576_CLKGATE_CON(61), 9, GFLAGS), + COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(61), 10, GFLAGS), + COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(61), 11, GFLAGS), + COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(147), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(61), 12, GFLAGS), + COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(147), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(61), 13, GFLAGS), + COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(147), 12, 1, MFLAGS, + RK3576_CLKGATE_CON(62), 0, GFLAGS), + COMPOSITE_NODIV(DCLK_VP2, "dclk_vp2", dclk_vp2_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(147), 13, 1, MFLAGS, + RK3576_CLKGATE_CON(62), 1, GFLAGS), + + /* vo0 */ + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(149), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(63), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(149), 7, 2, MFLAGS, + RK3576_CLKGATE_CON(63), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_150m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(149), 11, 2, MFLAGS, + RK3576_CLKGATE_CON(63), 3, GFLAGS), + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0, + RK3576_CLKGATE_CON(63), 12, GFLAGS), + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0, + RK3576_CLKGATE_CON(63), 13, GFLAGS), + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, + RK3576_CLKGATE_CON(63), 14, GFLAGS), + GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0, + RK3576_CLKGATE_CON(64), 4, GFLAGS), + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0, + RK3576_CLKGATE_CON(64), 5, GFLAGS), + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_spll_vpll_bpll_lpll_p, 0, + RK3576_CLKSEL_CON(151), 7, 3, MFLAGS, 0, 7, DFLAGS, + RK3576_CLKGATE_CON(64), 6, GFLAGS), + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0, + RK3576_CLKGATE_CON(64), 7, GFLAGS), + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(151), 15, 1, MFLAGS, 10, 5, DFLAGS, + RK3576_CLKGATE_CON(64), 8, GFLAGS), + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0, + RK3576_CLKGATE_CON(64), 9, GFLAGS), + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0, + RK3576_CLKGATE_CON(64), 13, GFLAGS), + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, + RK3576_CLKGATE_CON(64), 14, GFLAGS), + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(152), 1, 2, MFLAGS, + RK3576_CLKGATE_CON(64), 15, GFLAGS), + COMPOSITE(MCLK_SAI5_8CH_SRC, "mclk_sai5_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(154), 10, 3, MFLAGS, 2, 8, DFLAGS, + RK3576_CLKGATE_CON(65), 3, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI5_8CH, "mclk_sai5_8ch", mclk_sai5_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(154), 13, 1, MFLAGS, + RK3576_CLKGATE_CON(65), 4, GFLAGS), + GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0, + RK3576_CLKGATE_CON(65), 5, GFLAGS), + COMPOSITE(MCLK_SAI6_8CH_SRC, "mclk_sai6_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(155), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(65), 7, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI6_8CH, "mclk_sai6_8ch", mclk_sai6_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(155), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(65), 8, GFLAGS), + GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0, + RK3576_CLKGATE_CON(65), 9, GFLAGS), + GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0, + RK3576_CLKGATE_CON(65), 10, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX2, "mclk_spdif_tx2", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(156), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(65), 13, GFLAGS), + GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0, + RK3576_CLKGATE_CON(65), 14, GFLAGS), + COMPOSITE(MCLK_SPDIF_RX2, "mclk_spdif_rx2", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(156), 13, 2, MFLAGS, 8, 5, DFLAGS, + RK3576_CLKGATE_CON(65), 15, GFLAGS), + + /* vo1 */ + COMPOSITE(ACLK_VO1_ROOT, "aclk_vo1_root", gpll_cpll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(158), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(67), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(158), 7, 2, MFLAGS, + RK3576_CLKGATE_CON(67), 2, GFLAGS), + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(158), 9, 2, MFLAGS, + RK3576_CLKGATE_CON(67), 3, GFLAGS), + COMPOSITE(MCLK_SAI8_8CH_SRC, "mclk_sai8_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(157), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(66), 1, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI8_8CH, "mclk_sai8_8ch", mclk_sai8_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(157), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(66), 2, GFLAGS), + GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(66), 0, GFLAGS), + COMPOSITE(MCLK_SAI7_8CH_SRC, "mclk_sai7_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(159), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(67), 8, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI7_8CH, "mclk_sai7_8ch", mclk_sai7_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(159), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(67), 9, GFLAGS), + GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(67), 10, GFLAGS), + GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(67), 11, GFLAGS), + GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(67), 12, GFLAGS), + GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(67), 13, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX3, "mclk_spdif_tx3", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(160), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(67), 14, GFLAGS), + COMPOSITE_NOMUX(CLK_AUX16MHZ_0, "clk_aux16mhz_0", "gpll", 0, + RK3576_CLKSEL_CON(161), 0, 8, DFLAGS, + RK3576_CLKGATE_CON(67), 15, GFLAGS), + GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 0, GFLAGS), + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 1, GFLAGS), + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 4, GFLAGS), + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 5, GFLAGS), + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 6, GFLAGS), + GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0, + RK3576_CLKGATE_CON(68), 7, GFLAGS), + GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0, + RK3576_CLKGATE_CON(68), 9, GFLAGS), + COMPOSITE(MCLK_SAI9_8CH_SRC, "mclk_sai9_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(162), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(68), 10, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI9_8CH, "mclk_sai9_8ch", mclk_sai9_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(162), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(68), 11, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX4, "mclk_spdif_tx4", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(163), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(68), 12, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX5, "mclk_spdif_tx5", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(164), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(68), 13, GFLAGS), + + /* vpu */ + COMPOSITE(ACLK_VPU_ROOT, "aclk_vpu_root", gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(118), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(49), 0, GFLAGS), + COMPOSITE_NODIV(ACLK_VPU_MID_ROOT, "aclk_vpu_mid_root", mux_600m_400m_300m_24m_p, 0, + RK3576_CLKSEL_CON(118), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(49), 1, GFLAGS), + COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(118), 10, 2, MFLAGS, + RK3576_CLKGATE_CON(49), 2, GFLAGS), + COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, 0, + RK3576_CLKSEL_CON(119), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(49), 3, GFLAGS), + COMPOSITE_NODIV(ACLK_VPU_LOW_ROOT, "aclk_vpu_low_root", mux_400m_200m_100m_24m_p, 0, + RK3576_CLKSEL_CON(119), 7, 2, MFLAGS, + RK3576_CLKGATE_CON(49), 4, GFLAGS), + GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0, + RK3576_CLKGATE_CON(49), 13, GFLAGS), + GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0, + RK3576_CLKGATE_CON(49), 14, GFLAGS), + COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", gpll_spll_cpll_bpll_lpll_p, 0, + RK3576_CLKSEL_CON(120), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(49), 15, GFLAGS), + GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0, + RK3576_CLKGATE_CON(50), 0, GFLAGS), + GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0, + RK3576_CLKGATE_CON(50), 1, GFLAGS), + GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0, + RK3576_CLKGATE_CON(50), 2, GFLAGS), + GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0, + RK3576_CLKGATE_CON(50), 3, GFLAGS), + COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(120), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3576_CLKGATE_CON(50), 4, GFLAGS), + GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0, + RK3576_CLKGATE_CON(50), 5, GFLAGS), + GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0, + RK3576_CLKGATE_CON(50), 6, GFLAGS), + COMPOSITE(CLK_CORE_RGA2E_1, "clk_core_rga2e_1", gpll_spll_cpll_bpll_lpll_p, 0, + RK3576_CLKSEL_CON(121), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(50), 7, GFLAGS), + MUX(0, "dclk_ebc_frac_src_p", gpll_cpll_vpll_aupll_24m_p, 0, + RK3576_CLKSEL_CON(123), 0, 3, MFLAGS), + COMPOSITE_FRAC(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", "dclk_ebc_frac_src_p", 0, + RK3576_CLKSEL_CON(122), 0, + RK3576_CLKGATE_CON(50), 9, GFLAGS), + GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0, + RK3576_CLKGATE_CON(50), 11, GFLAGS), + GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0, + RK3576_CLKGATE_CON(50), 10, GFLAGS), + COMPOSITE(DCLK_EBC, "dclk_ebc", dclk_ebc_p, CLK_SET_RATE_NO_REPARENT, + RK3576_CLKSEL_CON(123), 12, 3, MFLAGS, 3, 9, DFLAGS, + RK3576_CLKGATE_CON(50), 12, GFLAGS), + + /* vepu */ + COMPOSITE_NODIV(HCLK_VEPU1_ROOT, "hclk_vepu1_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(178), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(78), 0, GFLAGS), + COMPOSITE(ACLK_VEPU1_ROOT, "aclk_vepu1_root", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(180), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(79), 0, GFLAGS), + GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0, + RK3576_CLKGATE_CON(79), 3, GFLAGS), + GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0, + RK3576_CLKGATE_CON(79), 4, GFLAGS), + COMPOSITE(CLK_VEPU1_CORE, "clk_vepu1_core", gpll_cpll_spll_lpll_bpll_p, 0, + RK3576_CLKSEL_CON(180), 11, 3, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(79), 5, GFLAGS), + + /* php */ + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(92), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(34), 0, GFLAGS), + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(92), 9, 1, MFLAGS, 4, 5, DFLAGS, + RK3576_CLKGATE_CON(34), 7, GFLAGS), + GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0, + RK3576_CLKGATE_CON(34), 13, GFLAGS), + GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0, + RK3576_CLKGATE_CON(34), 14, GFLAGS), + GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0, + RK3576_CLKGATE_CON(34), 15, GFLAGS), + GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 0, GFLAGS), + GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 1, GFLAGS), + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 3, GFLAGS), + GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0, + RK3576_CLKGATE_CON(35), 4, GFLAGS), + GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0, + RK3576_CLKGATE_CON(35), 5, GFLAGS), + GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 11, GFLAGS), + GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 13, GFLAGS), + GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0, + RK3576_CLKGATE_CON(35), 14, GFLAGS), + GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0, + RK3576_CLKGATE_CON(36), 0, GFLAGS), + GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0, + RK3576_CLKGATE_CON(36), 7, GFLAGS), + GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0, + RK3576_CLKGATE_CON(36), 8, GFLAGS), + GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0, + RK3576_CLKGATE_CON(36), 9, GFLAGS), + GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0, + RK3576_CLKGATE_CON(36), 10, GFLAGS), + GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0, + RK3576_CLKGATE_CON(36), 11, GFLAGS), + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(93), 7, 1, MFLAGS, 0, 7, DFLAGS, + RK3576_CLKGATE_CON(37), 0, GFLAGS), + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(93), 15, 1, MFLAGS, 8, 7, DFLAGS, + RK3576_CLKGATE_CON(37), 1, GFLAGS), + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(37), 2, GFLAGS), + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL, + RK3576_CLKGATE_CON(37), 3, GFLAGS), + GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0, + RK3576_CLKGATE_CON(37), 4, GFLAGS), + GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0, + RK3576_CLKGATE_CON(37), 5, GFLAGS), + + /* audio */ + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(42), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(7), 1, GFLAGS), + GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 3, GFLAGS), + GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 4, GFLAGS), + GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 5, GFLAGS), + GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 6, GFLAGS), + COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(42), 7, 2, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(7), 7, GFLAGS), + COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(42), 14, 2, MFLAGS, 9, 5, DFLAGS, + RK3576_CLKGATE_CON(7), 8, GFLAGS), + COMPOSITE(CLK_ASRC_4CH_0, "clk_asrc_4ch_0", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(43), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(7), 9, GFLAGS), + COMPOSITE(CLK_ASRC_4CH_1, "clk_asrc_4ch_1", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(43), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(7), 10, GFLAGS), + COMPOSITE(MCLK_SAI0_8CH_SRC, "mclk_sai0_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(44), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(7), 11, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI0_8CH, "mclk_sai0_8ch", mclk_sai0_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(44), 11, 2, MFLAGS, + RK3576_CLKGATE_CON(7), 12, GFLAGS), + GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 13, GFLAGS), + GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(7), 14, GFLAGS), + COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(45), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(7), 15, GFLAGS), + GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(8), 0, GFLAGS), + COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0, + RK3576_CLKSEL_CON(45), 12, 2, MFLAGS, 7, 5, DFLAGS, + RK3576_CLKGATE_CON(8), 1, GFLAGS), + COMPOSITE(MCLK_SAI1_8CH_SRC, "mclk_sai1_8ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(46), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(8), 4, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI1_8CH, "mclk_sai1_8ch", mclk_sai1_8ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(46), 11, 1, MFLAGS, + RK3576_CLKGATE_CON(8), 5, GFLAGS), + GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(8), 6, GFLAGS), + COMPOSITE(MCLK_SAI2_2CH_SRC, "mclk_sai2_2ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(47), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(8), 7, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI2_2CH, "mclk_sai2_2ch", mclk_sai2_2ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(47), 11, 2, MFLAGS, + RK3576_CLKGATE_CON(8), 8, GFLAGS), + GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(8), 10, GFLAGS), + COMPOSITE(MCLK_SAI3_2CH_SRC, "mclk_sai3_2ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(48), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(8), 11, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI3_2CH, "mclk_sai3_2ch", mclk_sai3_2ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(48), 11, 2, MFLAGS, + RK3576_CLKGATE_CON(8), 12, GFLAGS), + GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(8), 14, GFLAGS), + COMPOSITE(MCLK_SAI4_2CH_SRC, "mclk_sai4_2ch_src", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(49), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(8), 15, GFLAGS), + COMPOSITE_NODIV(MCLK_SAI4_2CH, "mclk_sai4_2ch", mclk_sai4_2ch_p, CLK_SET_RATE_PARENT, + RK3576_CLKSEL_CON(49), 11, 2, MFLAGS, + RK3576_CLKGATE_CON(9), 0, GFLAGS), + GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(9), 2, GFLAGS), + GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(9), 3, GFLAGS), + GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0, + RK3576_CLKGATE_CON(9), 4, GFLAGS), + COMPOSITE(CLK_PDM1, "clk_pdm1", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(50), 9, 3, MFLAGS, 0, 9, DFLAGS, + RK3576_CLKGATE_CON(9), 5, GFLAGS), + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(9), 7, GFLAGS), + GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0, + RK3576_CLKGATE_CON(3), 5, GFLAGS), + COMPOSITE(MCLK_PDM1, "mclk_pdm1", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(51), 5, 3, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(9), 8, GFLAGS), + GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(9), 9, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX0, "mclk_spdif_tx0", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(52), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(9), 10, GFLAGS), + GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0, + RK3576_CLKGATE_CON(9), 11, GFLAGS), + COMPOSITE(MCLK_SPDIF_TX1, "mclk_spdif_tx1", audio_frac_int_p, 0, + RK3576_CLKSEL_CON(53), 8, 3, MFLAGS, 0, 8, DFLAGS, + RK3576_CLKGATE_CON(9), 12, GFLAGS), + GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0, + RK3576_CLKGATE_CON(9), 13, GFLAGS), + GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0, + RK3576_CLKGATE_CON(9), 14, GFLAGS), + GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0, + RK3576_CLKGATE_CON(9), 15, GFLAGS), + GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0, + RK3576_CLKGATE_CON(10), 0, GFLAGS), + GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0, + RK3576_CLKGATE_CON(10), 1, GFLAGS), + + /* sdgmac */ + COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", mux_200m_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(103), 0, 2, MFLAGS, + RK3576_CLKGATE_CON(42), 0, GFLAGS), + COMPOSITE(ACLK_SDGMAC_ROOT, "aclk_sdgmac_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(103), 7, 1, MFLAGS, 2, 5, DFLAGS, + RK3576_CLKGATE_CON(42), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_SDGMAC_ROOT, "pclk_sdgmac_root", mux_100m_50m_24m_p, 0, + RK3576_CLKSEL_CON(103), 8, 2, MFLAGS, + RK3576_CLKGATE_CON(42), 2, GFLAGS), + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(42), 7, GFLAGS), + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(42), 8, GFLAGS), + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(42), 9, GFLAGS), + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(42), 10, GFLAGS), + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(104), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3576_CLKGATE_CON(42), 11, GFLAGS), + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(42), 12, GFLAGS), + COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", clk_gmac1_ptp_ref_src_p, 0, + RK3576_CLKSEL_CON(104), 13, 2, MFLAGS, 8, 5, DFLAGS, + RK3576_CLKGATE_CON(42), 15, GFLAGS), + COMPOSITE(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", clk_gmac0_ptp_ref_src_p, 0, + RK3576_CLKSEL_CON(105), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(43), 0, GFLAGS), + GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", 0, + RK3576_CLKGATE_CON(42), 13, GFLAGS), + GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", 0, + RK3576_CLKGATE_CON(42), 14, GFLAGS), + COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(105), 13, 2, MFLAGS, 7, 6, DFLAGS, + RK3576_CLKGATE_CON(43), 1, GFLAGS), + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(43), 2, GFLAGS), + COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(106), 6, 2, MFLAGS, 0, 6, DFLAGS, + RK3576_CLKGATE_CON(43), 3, GFLAGS), + GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(43), 4, GFLAGS), + COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, CLK_IS_CRITICAL, + RK3576_CLKSEL_CON(106), 13, 1, MFLAGS, 8, 5, DFLAGS, + RK3576_CLKGATE_CON(43), 5, GFLAGS), + GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0, + RK3576_CLKGATE_CON(43), 7, GFLAGS), + GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(43), 8, GFLAGS), + COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_p, 0, + RK3576_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(43), 9, GFLAGS), + GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(43), 10, GFLAGS), + COMPOSITE(CLK_HSGPIO_TX, "clk_hsgpio_tx", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, + RK3576_CLKGATE_CON(43), 11, GFLAGS), + COMPOSITE(CLK_HSGPIO_RX, "clk_hsgpio_rx", gpll_cpll_24m_p, 0, + RK3576_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, + RK3576_CLKGATE_CON(43), 12, GFLAGS), + GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0, + RK3576_CLKGATE_CON(43), 13, GFLAGS), + + /* phpphy */ + GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", CLK_IS_CRITICAL, + RK3576_PHP_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", "pclk_phpphy_root", 0, + RK3576_PHP_CLKGATE_CON(0), 5, GFLAGS), + GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", "pclk_phpphy_root", 0, + RK3576_PHP_CLKGATE_CON(0), 7, GFLAGS), + COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0, + RK3576_PHP_CLKSEL_CON(0), 2, 5, DFLAGS, + RK3576_PHP_CLKGATE_CON(1), 1, GFLAGS), + COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", "ppll", 0, + RK3576_PHP_CLKSEL_CON(0), 7, 5, DFLAGS, + RK3576_PHP_CLKGATE_CON(1), 2, GFLAGS), + COMPOSITE_NODIV(CLK_REF_PCIE0_PHY, "clk_ref_pcie0_phy", clk_ref_pcie0_phy_p, 0, + RK3576_PHP_CLKSEL_CON(0), 12, 2, MFLAGS, + RK3576_PHP_CLKGATE_CON(1), 5, GFLAGS), + COMPOSITE_NODIV(CLK_REF_PCIE1_PHY, "clk_ref_pcie1_phy", clk_ref_pcie0_phy_p, 0, + RK3576_PHP_CLKSEL_CON(0), 14, 2, MFLAGS, + RK3576_PHP_CLKGATE_CON(1), 8, GFLAGS), + COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", CLK_IS_CRITICAL, + RK3576_PHP_CLKSEL_CON(1), 0, 8, DFLAGS, + RK3576_PHP_CLKGATE_CON(1), 9, GFLAGS), + + /* pmu */ + GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0, + RK3576_PMU_CLKGATE_CON(3), 2, GFLAGS), + COMPOSITE_NOMUX(CLK_100M_PMU_SRC, "clk_100m_pmu_src", "cpll", 0, + RK3576_PMU_CLKSEL_CON(4), 4, 5, DFLAGS, + RK3576_PMU_CLKGATE_CON(3), 3, GFLAGS), + FACTOR_GATE(CLK_50M_PMU_SRC, "clk_50m_pmu_src", "clk_100m_pmu_src", 0, 1, 2, + RK3576_PMU_CLKGATE_CON(3), 4, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL, + RK3576_PMU_CLKSEL_CON(4), 0, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(3), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, + RK3576_PMU_CLKSEL_CON(4), 2, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(3), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", mux_pmu100m_pmu50m_24m_p, 0, + RK3576_PMU_CLKSEL_CON(20), 0, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(7), 0, GFLAGS), + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(7), 3, GFLAGS), + GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(7), 9, GFLAGS), + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(3), 15, GFLAGS), + GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS), + GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS), + GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS), + GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS), + GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(0), 8, GFLAGS), + GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(0), 12, GFLAGS), + COMPOSITE_NOMUX(CLK_PMUPHY_REF_SRC, "clk_pmuphy_ref_src", "cpll", 0, + RK3576_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, + RK3576_PMU_CLKGATE_CON(0), 13, GFLAGS), + GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", "xin24m", 0, + RK3576_PMU_CLKGATE_CON(0), 15, GFLAGS), + GATE(CLK_HDMITXHPD, "clk_hdmitxhpd", "xin24m", 0, + RK3576_PMU_CLKGATE_CON(1), 13, GFLAGS), + GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0, + RK3576_PMU_CLKGATE_CON(2), 0, GFLAGS), + MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0, + RK3576_PMU_CLKSEL_CON(3), 0, 2, MFLAGS), + GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0, + RK3576_PMU_CLKGATE_CON(2), 5, GFLAGS), + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0, + RK3576_PMU_CLKGATE_CON(3), 12, GFLAGS), + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, 0, + RK3576_PMU_CLKSEL_CON(4), 14, 1, MFLAGS, 9, 5, DFLAGS, + RK3576_PMU_CLKGATE_CON(3), 14, GFLAGS), + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(4), 5, GFLAGS), + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, + RK3576_PMU_CLKSEL_CON(4), 15, 1, MFLAGS, + RK3576_PMU_CLKGATE_CON(4), 6, GFLAGS), + GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(4), 7, GFLAGS), + COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", mux_pmu100m_24m_32k_p, 0, + RK3576_PMU_CLKSEL_CON(5), 0, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(4), 8, GFLAGS), + GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0, + RK3576_PMU_CLKGATE_CON(4), 9, GFLAGS), + GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0, + RK3576_PMU_CLKGATE_CON(4), 10, GFLAGS), + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(4), 11, GFLAGS), + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", mux_pmu100m_pmu50m_24m_p, 0, + RK3576_PMU_CLKSEL_CON(5), 2, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(4), 12, GFLAGS), + GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0, + RK3576_PMU_CLKGATE_CON(4), 13, GFLAGS), + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(5), 1, GFLAGS), + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", mux_pmu200m_pmu100m_pmu50m_24m_p, 0, + RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS, + RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS), + COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0, + RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS, + RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS), + GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(5), 6, GFLAGS), + GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0, + RK3576_PMU_CLKGATE_CON(5), 13, GFLAGS), + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(5), 15, GFLAGS), + GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0, + RK3576_PMU_CLKGATE_CON(6), 0, GFLAGS), + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, + RK3576_PMU_CLKGATE_CON(6), 1, GFLAGS), + GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0, + RK3576_PMU_CLKGATE_CON(6), 8, GFLAGS), + COMPOSITE(CLK_HPTIMER_SRC, "clk_hptimer_src", cpll_24m_p, CLK_IS_CRITICAL, + RK3576_PMU_CLKSEL_CON(11), 6, 1, MFLAGS, 1, 5, DFLAGS, + RK3576_PMU_CLKGATE_CON(6), 10, GFLAGS), + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, + RK3576_PMU_CLKGATE_CON(7), 6, GFLAGS), + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, + RK3576_PMU_CLKSEL_CON(20), 2, 1, MFLAGS, + RK3576_PMU_CLKGATE_CON(7), 7, GFLAGS), + GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL, + RK3576_PMU_CLKGATE_CON(7), 8, GFLAGS), + GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0, + RK3576_PMU_CLKGATE_CON(5), 7, GFLAGS), + + /* phy ref */ + MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0, + RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS), + MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", clk_usbphy_ref_src_p, 0, + RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS), + MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0, + RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS), + MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, 0, + RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS), + + /* secure ns */ + COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL, + RK3576_SECURE_NS_CLKSEL_CON(0), 0, 2, MFLAGS, + RK3576_SECURE_NS_CLKGATE_CON(0), 0, GFLAGS), + COMPOSITE_NODIV(HCLK_SECURE_NS, "hclk_secure_ns", mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL, + RK3576_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS, + RK3576_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS), + COMPOSITE_NODIV(PCLK_SECURE_NS, "pclk_secure_ns", mux_116m_58m_24m_p, CLK_IS_CRITICAL, + RK3576_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS, + RK3576_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS), + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0, + RK3576_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS), + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0, + RK3576_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS), + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, + RK3576_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS), + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0, + RK3576_NON_SECURE_GATING_CON00, 14, GFLAGS), + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0, + RK3576_NON_SECURE_GATING_CON00, 13, GFLAGS), + GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0, + RK3576_NON_SECURE_GATING_CON00, 1, GFLAGS), + + /* io */ + GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0, + RK3576_CLKGATE_CON(59), 1, GFLAGS), + GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0, + RK3576_CLKGATE_CON(59), 2, GFLAGS), + GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0, + RK3576_CLKGATE_CON(59), 3, GFLAGS), + GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0, + RK3576_CLKGATE_CON(59), 4, GFLAGS), + GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0, + RK3576_CLKGATE_CON(59), 5, GFLAGS), +}; + +static void __init rk3576_clk_init(struct device_node *np) +{ + struct rockchip_clk_provider *ctx; + unsigned long clk_nr_clks; + void __iomem *reg_base; + struct regmap *grf; + + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches, + ARRAY_SIZE(rk3576_clk_branches)) + 1; + + grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf"); + if (IS_ERR(grf)) { + pr_err("%s: could not get PMU0 GRF syscon\n", __func__); + return; + } + + reg_base = of_iomap(np, 0); + if (!reg_base) { + pr_err("%s: could not map cru region\n", __func__); + return; + } + + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); + if (IS_ERR(ctx)) { + pr_err("%s: rockchip clk init failed\n", __func__); + iounmap(reg_base); + return; + } + + ctx->grf = grf; + + rockchip_clk_register_plls(ctx, rk3576_pll_clks, + ARRAY_SIZE(rk3576_pll_clks), + RK3576_GRF_SOC_STATUS0); + + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), + &rk3576_cpulclk_data, rk3576_cpulclk_rates, + ARRAY_SIZE(rk3576_cpulclk_rates)); + rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b", + mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), + &rk3576_cpubclk_data, rk3576_cpubclk_rates, + ARRAY_SIZE(rk3576_cpubclk_rates)); + + rockchip_clk_register_branches(ctx, rk3576_clk_branches, + ARRAY_SIZE(rk3576_clk_branches)); + + rk3576_rst_init(np, reg_base); + + rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL); + + rockchip_clk_of_add_provider(np, ctx); +} + +CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init); + +#ifdef MODULE +struct clk_rk3576_inits { + void (*inits)(struct device_node *np); +}; + +static const struct clk_rk3576_inits clk_rk3576_cru_init = { + .inits = rk3576_clk_init, +}; + +static const struct of_device_id clk_rk3576_match_table[] = { + { + .compatible = "rockchip,rk3576-cru", + .data = &clk_rk3576_cru_init, + }, + { } +}; +MODULE_DEVICE_TABLE(of, clk_rk3576_match_table); + +static int clk_rk3576_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + const struct of_device_id *match; + const struct clk_rk3576_inits *init_data; + + match = of_match_device(clk_rk3576_match_table, &pdev->dev); + if (!match || !match->data) + return -EINVAL; + + init_data = match->data; + if (init_data->inits) + init_data->inits(np); + + return 0; +} + +static struct platform_driver clk_rk3576_driver = { + .probe = clk_rk3576_probe, + .driver = { + .name = "clk-rk3576", + .of_match_table = clk_rk3576_match_table, + .suppress_bind_attrs = true, + }, +}; +module_platform_driver(clk_rk3576_driver); + +MODULE_DESCRIPTION("Rockchip RK3576 Clock Driver"); +MODULE_LICENSE("GPL"); +#endif /* MODULE */ diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index 40fc0e4703c1..f1957e1c1178 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -235,6 +235,58 @@ struct clk; #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) +#define RK3576_PHP_CRU_BASE 0x8000 +#define RK3576_SECURE_NS_CRU_BASE 0x10000 +#define RK3576_PMU_CRU_BASE 0x20000 +#define RK3576_BIGCORE_CRU_BASE 0x38000 +#define RK3576_LITCORE_CRU_BASE 0x40000 +#define RK3576_CCI_CRU_BASE 0x48000 + +#define RK3576_PLL_CON(x) RK2928_PLL_CON(x) +#define RK3576_MODE_CON0 0x280 +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) +#define RK3576_GLB_CNT_TH 0xc00 +#define RK3576_GLB_SRST_FST 0xc08 +#define RK3576_GLB_SRST_SND 0xc0c +#define RK3576_GLB_RST_CON 0xc10 +#define RK3576_GLB_RST_ST 0xc04 +#define RK3576_SDIO_CON0 0xC24 +#define RK3576_SDIO_CON1 0xC28 +#define RK3576_SDMMC_CON0 0xC30 +#define RK3576_SDMMC_CON1 0xC34 + +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x300) +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0x800) +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + 0xa00) + +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x300) +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0x800) +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + 0xa00) + +#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x300) +#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0x800) +#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + RK3576_SECURE_NS_CRU_BASE + 0xa00) + +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x300) +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0x800) +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + 0xa00) + +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x300) +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0x800) +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE + 0xa00) +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x300) +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0x800) +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + RK3576_LITCORE_CRU_BASE + 0xa00) +#define RK3576_NON_SECURE_GATING_CON00 0xc48 + #define RK3588_PHP_CRU_BASE 0x8000 #define RK3588_PMU_CRU_BASE 0x30000 #define RK3588_BIGCORE0_CRU_BASE 0x50000 @@ -1026,6 +1078,7 @@ static inline void rockchip_register_softrst(struct device_node *np, return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags); } +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); #endif diff --git a/drivers/clk/rockchip/rst-rk3576.c b/drivers/clk/rockchip/rst-rk3576.c new file mode 100644 index 000000000000..3380d73c86c5 --- /dev/null +++ b/drivers/clk/rockchip/rst-rk3576.c @@ -0,0 +1,652 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + * Copyright (c) 2024 Collabora Ltd. + * Author: Detlev Casanova <detlev.casanova@collabora.com> + * Based on Sebastien Reichel's implementation for RK3588 + */ + +#include <linux/module.h> +#include <linux/of.h> +#include <dt-bindings/reset/rockchip,rk3576-cru.h> +#include "clk.h" + +/* 0x27200000 + 0x0A00 */ +#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit) +/* 0x27208000 + 0x0A00 */ +#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit) +/* 0x27210000 + 0x0A00 */ +#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit) +/* 0x27220000 + 0x0A00 */ +#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + reg * 16 + bit) + +/* mapping table for reset ID to register offset */ +static const int rk3576_register_offset[] = { + /* SOFTRST_CON01 */ + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), + + /* SOFTRST_CON02 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), + + /* SOFTRST_CON06 */ + RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), + + /* SOFTRST_CON07 */ + RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), + + /* SOFTRST_CON08 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), + + /* SOFTRST_CON09 */ + RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), + RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), + RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), + RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), + + /* SOFTRST_CON11 */ + RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), + RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), + RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), + RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), + + /* SOFTRST_CON12 */ + RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), + RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), + RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), + RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), + RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), + + /* SOFTRST_CON13 */ + RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), + RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), + RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), + RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), + RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), + RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), + RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), + + /* SOFTRST_CON14 */ + RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), + RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), + RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), + RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), + RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), + RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), + + /* SOFTRST_CON15 */ + RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), + RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), + RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), + RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), + RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), + RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), + + /* SOFTRST_CON16 */ + RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), + RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), + RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), + RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), + RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), + RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), + RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), + + /* SOFTRST_CON17 */ + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), + RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), + RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), + RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), + RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), + RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), + RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), + RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), + + /* SOFTRST_CON18 */ + RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), + RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), + RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), + RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), + RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), + RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), + RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), + RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), + RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), + RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), + + /* SOFTRST_CON19 */ + RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), + RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), + RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), + + /* SOFTRST_CON20 */ + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), + RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), + RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), + RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), + RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), + RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), + + /* SOFTRST_CON21 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), + + /* SOFTRST_CON22 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), + RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), + + /* SOFTRST_CON23 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), + RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), + + /* SOFTRST_CON25 */ + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), + + /* SOFTRST_CON26 */ + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), + + /* SOFTRST_CON27 */ + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), + + /* SOFTRST_CON28 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), + + /* SOFTRST_CON29 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), + + /* SOFTRST_CON31 */ + RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), + RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), + + /* SOFTRST_CON32 */ + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), + RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), + RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), + RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), + RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), + RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), + + /* SOFTRST_CON33 */ + RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), + RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), + RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), + RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), + RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), + + /* SOFTRST_CON34 */ + RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), + RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), + + /* SOFTRST_CON35 */ + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), + + /* SOFTRST_CON36 */ + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), + RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), + + /* SOFTRST_CON37 */ + RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), + RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), + RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), + RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), + + /* SOFTRST_CON40 */ + RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), + RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), + + /* SOFTRST_CON42 */ + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), + + /* SOFTRST_CON43 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), + RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), + + /* SOFTRST_CON45 */ + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), + + /* SOFTRST_CON47 */ + RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), + + /* SOFTRST_CON48 */ + RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), + + /* SOFTRST_CON49 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), + RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), + + /* SOFTRST_CON50 */ + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), + RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), + RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), + RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), + RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), + + /* SOFTRST_CON51 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), + RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), + + /* SOFTRST_CON53 */ + RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), + RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), + RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), + RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), + RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), + + /* SOFTRST_CON54 */ + RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), + + /* SOFTRST_CON59 */ + RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), + + /* SOFTRST_CON61 */ + RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), + RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), + RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), + RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), + + /* SOFTRST_CON62 */ + RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), + RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), + RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), + RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), + + /* SOFTRST_CON63 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), + RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), + + /* SOFTRST_CON64 */ + RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), + RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), + RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), + RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), + RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), + + /* SOFTRST_CON65 */ + RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), + + /* SOFTRST_CON66 */ + RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), + + /* SOFTRST_CON67 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), + + /* SOFTRST_CON68 */ + RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), + RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), + RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), + RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), + + /* SOFTRST_CON69 */ + RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), + RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), + + /* SOFTRST_CON72 */ + RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), + RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), + RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), + RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), + RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), + + /* SOFTRST_CON75 */ + RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), + + /* SOFTRST_CON78 */ + RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), + RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), + RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), + RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), + + /* SOFTRST_CON79 */ + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), + RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), + + /* PPLL_SOFTRST_CON00 */ + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), + + /* PPLL_SOFTRST_CON01 */ + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), + + /* SECURENS_SOFTRST_CON00 */ + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), + RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), + + /* PMU1_SOFTRST_CON00 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), + + /* PMU1_SOFTRST_CON01 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHPD, 1, 13), + + /* PMU1_SOFTRST_CON02 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), + + /* PMU1_SOFTRST_CON03 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), + + /* PMU1_SOFTRST_CON04 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), + + /* PMU1_SOFTRST_CON05 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), + RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), + + /* PMU1_SOFTRST_CON06 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), + + /* PMU1_SOFTRST_CON07 */ + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), + RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), +}; + +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base) +{ + rockchip_register_softrst_lut(np, + rk3576_register_offset, + ARRAY_SIZE(rk3576_register_offset), + reg_base + RK3576_SOFTRST_CON(0), + ROCKCHIP_SOFTRST_HIWORD_MASK); +} + -- 2.46.0 ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 2024-08-22 19:49 ` [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 Detlev Casanova @ 2024-08-23 5:16 ` Dragan Simic 0 siblings, 0 replies; 8+ messages in thread From: Dragan Simic @ 2024-08-23 5:16 UTC (permalink / raw) To: Detlev Casanova Cc: linux-kernel, Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner, Philipp Zabel, Elaine Zhang, linux-clk, devicetree, linux-arm-kernel, linux-rockchip, kernel, Finley Xiao, YouMin Chen, Liang Chen, Sugar Zhang, Shawn Lin Hello Detlev, On 2024-08-22 21:49, Detlev Casanova wrote: > From: Elaine Zhang <zhangqing@rock-chips.com> > > Add the clock and reset tree definitions for the new RK3576 > SoC. > > As opposed to the other rockchip CRU drivers, the GRF node is looked up > via compatible instead of a phandle, which simplifies the device tree > bindings. > > Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com> > Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> > Signed-off-by: YouMin Chen <cym@rock-chips.com> > Signed-off-by: Liang Chen <cl@rock-chips.com> > Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com> > Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com> > Reviewed-by: Elaine Zhang <zhangqing@rock-chips.com> > Tested-by: Shawn Lin <shawn.lin@rock-chips.com> Thanks for the patch. I had a rather detailed look at the patch, while focusing on having no regressions introduced, and I found none. So, please feel free to include: Acked-by: Dragan Simic <dsimic@manjaro.org> > --- > drivers/clk/rockchip/Kconfig | 7 + > drivers/clk/rockchip/Makefile | 1 + > drivers/clk/rockchip/clk-rk3576.c | 1829 +++++++++++++++++++++++++++++ > drivers/clk/rockchip/clk.h | 53 + > drivers/clk/rockchip/rst-rk3576.c | 652 ++++++++++ > 5 files changed, 2542 insertions(+) > create mode 100644 drivers/clk/rockchip/clk-rk3576.c > create mode 100644 drivers/clk/rockchip/rst-rk3576.c > > diff --git a/drivers/clk/rockchip/Kconfig > b/drivers/clk/rockchip/Kconfig > index 9aad86925cd2..f8eb16f170d4 100644 > --- a/drivers/clk/rockchip/Kconfig > +++ b/drivers/clk/rockchip/Kconfig > @@ -100,6 +100,13 @@ config CLK_RK3568 > help > Build the driver for RK3568 Clock Driver. > > +config CLK_RK3576 > + tristate "Rockchip RK3576 clock controller support" > + depends on ARM64 || COMPILE_TEST > + default y > + help > + Build the driver for RK3576 Clock Driver. > + > config CLK_RK3588 > bool "Rockchip RK3588 clock controller support" > depends on ARM64 || COMPILE_TEST > diff --git a/drivers/clk/rockchip/Makefile > b/drivers/clk/rockchip/Makefile > index 36894f6a7022..af2ade54a7ef 100644 > --- a/drivers/clk/rockchip/Makefile > +++ b/drivers/clk/rockchip/Makefile > @@ -28,4 +28,5 @@ obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o > obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o > obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o > obj-$(CONFIG_CLK_RK3568) += clk-rk3568.o > +obj-$(CONFIG_CLK_RK3576) += clk-rk3576.o rst-rk3576.o > obj-$(CONFIG_CLK_RK3588) += clk-rk3588.o rst-rk3588.o > diff --git a/drivers/clk/rockchip/clk-rk3576.c > b/drivers/clk/rockchip/clk-rk3576.c > new file mode 100644 > index 000000000000..a002b119cc6b > --- /dev/null > +++ b/drivers/clk/rockchip/clk-rk3576.c > @@ -0,0 +1,1829 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2023 Rockchip Electronics Co. Ltd. > + * Author: Elaine Zhang <zhangqing@rock-chips.com> > + */ > + > +#include <linux/clk-provider.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/of_address.h> > +#include <linux/syscore_ops.h> > +#include <linux/mfd/syscon.h> > +#include <dt-bindings/clock/rockchip,rk3576-cru.h> > +#include "clk.h" > + > +#define RK3576_GRF_SOC_STATUS0 0x600 > +#define RK3576_PMU0_GRF_OSC_CON6 0x18 > + > +enum rk3576_plls { > + bpll, lpll, vpll, aupll, cpll, gpll, ppll, > +}; > + > +static struct rockchip_pll_rate_table rk3576_pll_rates[] = { > + /* _mhz, _p, _m, _s, _k */ > + RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), > + RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), > + RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), > + RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), > + RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), > + RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), > + RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), > + RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), > + RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), > + RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), > + RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), > + RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), > + RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), > + RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), > + RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), > + RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), > + RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), > + RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), > + RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), > + RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), > + RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), > + RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), > + RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), > + RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), > + RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), > + RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), > + RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), > + RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), > + RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), > + RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), > + RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), > + RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), > + RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), > + RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), > + RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), > + RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), > + RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), > + RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), > + RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), > + RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), > + RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), > + RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), > + RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), > + RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), > + RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), > + RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), > + RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), > + RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), > + RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), > + RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), > + RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), > + RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), > + RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), > + RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), > + RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), > + RK3588_PLL_RATE(955520000, 3, 477, 2, 49806), > + RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), > + RK3588_PLL_RATE(900000000, 2, 300, 2, 0), > + RK3588_PLL_RATE(816000000, 2, 272, 2, 0), > + RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), > + RK3588_PLL_RATE(786000000, 1, 131, 2, 0), > + RK3588_PLL_RATE(785560000, 3, 392, 2, 51117), > + RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), > + RK3588_PLL_RATE(600000000, 2, 200, 2, 0), > + RK3588_PLL_RATE(594000000, 2, 198, 2, 0), > + RK3588_PLL_RATE(408000000, 2, 272, 3, 0), > + RK3588_PLL_RATE(312000000, 2, 208, 3, 0), > + RK3588_PLL_RATE(216000000, 2, 288, 4, 0), > + RK3588_PLL_RATE(96000000, 2, 256, 5, 0), > + { /* sentinel */ }, > +}; > + > +static struct rockchip_pll_rate_table rk3576_ppll_rates[] = { > + /* _mhz, _p, _m, _s, _k */ > + RK3588_PLL_RATE(1300000000, 3, 325, 2, 0), > + { /* sentinel */ }, > +}; > + > +#define RK3576_ACLK_M_BIGCORE_DIV_MASK 0x1f > +#define RK3576_ACLK_M_BIGCORE_DIV_SHIFT 0 > +#define RK3576_ACLK_M_LITCORE_DIV_MASK 0x1f > +#define RK3576_ACLK_M_LITCORE_DIV_SHIFT 8 > +#define RK3576_PCLK_DBG_LITCORE_DIV_MASK 0x1f > +#define RK3576_PCLK_DBG_LITCORE_DIV_SHIFT 0 > +#define RK3576_ACLK_CCI_DIV_MASK 0x1f > +#define RK3576_ACLK_CCI_DIV_SHIFT 7 > +#define RK3576_ACLK_CCI_MUX_MASK 0x3 > +#define RK3576_ACLK_CCI_MUX_SHIFT 12 > + > +#define RK3576_BIGCORE_CLKSEL2(_amcore) \ > +{ \ > + .reg = RK3576_BIGCORE_CLKSEL_CON(2), \ > + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_BIGCORE_DIV_MASK, \ > + RK3576_ACLK_M_BIGCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_LITCORE_CLKSEL1(_amcore) \ > +{ \ > + .reg = RK3576_LITCORE_CLKSEL_CON(1), \ > + .val = HIWORD_UPDATE(_amcore - 1, RK3576_ACLK_M_LITCORE_DIV_MASK, \ > + RK3576_ACLK_M_LITCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_LITCORE_CLKSEL2(_pclkdbg) \ > +{ \ > + .reg = RK3576_LITCORE_CLKSEL_CON(2), \ > + .val = HIWORD_UPDATE(_pclkdbg - 1, > RK3576_PCLK_DBG_LITCORE_DIV_MASK, \ > + RK3576_PCLK_DBG_LITCORE_DIV_SHIFT), \ > +} > + > +#define RK3576_CCI_CLKSEL4(_ccisel, _div) \ > +{ \ > + .reg = RK3576_CCI_CLKSEL_CON(4), \ > + .val = HIWORD_UPDATE(_ccisel, RK3576_ACLK_CCI_MUX_MASK, \ > + RK3576_ACLK_CCI_MUX_SHIFT) | \ > + HIWORD_UPDATE(_div - 1, RK3576_ACLK_CCI_DIV_MASK, \ > + RK3576_ACLK_CCI_DIV_SHIFT), \ > +} > + > +#define RK3576_CPUBCLK_RATE(_prate, _amcore) \ > +{ \ > + .prate = _prate##U, \ > + .divs = { \ > + RK3576_BIGCORE_CLKSEL2(_amcore), \ > + }, \ > +} > + > +#define RK3576_CPULCLK_RATE(_prate, _amcore, _pclkdbg, _ccisel) \ > +{ \ > + .prate = _prate##U, \ > + .divs = { \ > + RK3576_LITCORE_CLKSEL1(_amcore), \ > + RK3576_LITCORE_CLKSEL2(_pclkdbg), \ > + }, \ > + .pre_muxs = { \ > + RK3576_CCI_CLKSEL4(2, 2), \ > + }, \ > + .post_muxs = { \ > + RK3576_CCI_CLKSEL4(_ccisel, 2), \ > + }, \ > +} > + > +static struct rockchip_cpuclk_rate_table rk3576_cpubclk_rates[] > __initdata = { > + RK3576_CPUBCLK_RATE(2496000000, 2), > + RK3576_CPUBCLK_RATE(2400000000, 2), > + RK3576_CPUBCLK_RATE(2304000000, 2), > + RK3576_CPUBCLK_RATE(2208000000, 2), > + RK3576_CPUBCLK_RATE(2184000000, 2), > + RK3576_CPUBCLK_RATE(2088000000, 2), > + RK3576_CPUBCLK_RATE(2040000000, 2), > + RK3576_CPUBCLK_RATE(2016000000, 2), > + RK3576_CPUBCLK_RATE(1992000000, 2), > + RK3576_CPUBCLK_RATE(1896000000, 2), > + RK3576_CPUBCLK_RATE(1800000000, 2), > + RK3576_CPUBCLK_RATE(1704000000, 2), > + RK3576_CPUBCLK_RATE(1608000000, 2), > + RK3576_CPUBCLK_RATE(1584000000, 2), > + RK3576_CPUBCLK_RATE(1560000000, 2), > + RK3576_CPUBCLK_RATE(1536000000, 2), > + RK3576_CPUBCLK_RATE(1512000000, 2), > + RK3576_CPUBCLK_RATE(1488000000, 2), > + RK3576_CPUBCLK_RATE(1464000000, 2), > + RK3576_CPUBCLK_RATE(1440000000, 2), > + RK3576_CPUBCLK_RATE(1416000000, 2), > + RK3576_CPUBCLK_RATE(1392000000, 2), > + RK3576_CPUBCLK_RATE(1368000000, 2), > + RK3576_CPUBCLK_RATE(1344000000, 2), > + RK3576_CPUBCLK_RATE(1320000000, 2), > + RK3576_CPUBCLK_RATE(1296000000, 2), > + RK3576_CPUBCLK_RATE(1272000000, 2), > + RK3576_CPUBCLK_RATE(1248000000, 2), > + RK3576_CPUBCLK_RATE(1224000000, 2), > + RK3576_CPUBCLK_RATE(1200000000, 2), > + RK3576_CPUBCLK_RATE(1104000000, 2), > + RK3576_CPUBCLK_RATE(1008000000, 2), > + RK3576_CPUBCLK_RATE(912000000, 2), > + RK3576_CPUBCLK_RATE(816000000, 2), > + RK3576_CPUBCLK_RATE(696000000, 2), > + RK3576_CPUBCLK_RATE(600000000, 2), > + RK3576_CPUBCLK_RATE(408000000, 2), > + RK3576_CPUBCLK_RATE(312000000, 2), > + RK3576_CPUBCLK_RATE(216000000, 2), > + RK3576_CPUBCLK_RATE(96000000, 2), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3576_cpubclk_data = { > + .core_reg[0] = RK3576_BIGCORE_CLKSEL_CON(1), > + .div_core_shift[0] = 7, > + .div_core_mask[0] = 0x1f, > + .num_cores = 1, > + .mux_core_alt = 1, > + .mux_core_main = 0, > + .mux_core_shift = 12, > + .mux_core_mask = 0x3, > +}; > + > +static struct rockchip_cpuclk_rate_table rk3576_cpulclk_rates[] > __initdata = { > + RK3576_CPULCLK_RATE(2400000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2304000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2208000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2184000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2088000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2040000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(2016000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1992000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1896000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1800000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1704000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1608000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1584000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1560000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1536000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1512000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1488000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1464000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1440000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1416000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1392000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1368000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1344000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1320000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1296000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1272000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1248000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1224000000, 2, 6, 3), > + RK3576_CPULCLK_RATE(1200000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(1104000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(1008000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(912000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(816000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(696000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(600000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(408000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(312000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(216000000, 2, 6, 2), > + RK3576_CPULCLK_RATE(96000000, 2, 6, 2), > +}; > + > +static const struct rockchip_cpuclk_reg_data rk3576_cpulclk_data = { > + .core_reg[0] = RK3576_LITCORE_CLKSEL_CON(0), > + .div_core_shift[0] = 7, > + .div_core_mask[0] = 0x1f, > + .num_cores = 1, > + .mux_core_alt = 1, > + .mux_core_main = 0, > + .mux_core_shift = 12, > + .mux_core_mask = 0x3, > +}; > + > +#define MFLAGS CLK_MUX_HIWORD_MASK > +#define DFLAGS CLK_DIVIDER_HIWORD_MASK > +#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE) > + > +PNAME(mux_pll_p) = { "xin24m", "xin32k" }; > +PNAME(mux_24m_32k_p) = { "xin24m", "xin_osc0_div" }; > +PNAME(mux_armclkl_p) = { "xin24m", "pll_lpll", "lpll" }; > +PNAME(mux_armclkb_p) = { "xin24m", "pll_bpll", "bpll" }; > +PNAME(gpll_24m_p) = { "gpll", "xin24m" }; > +PNAME(cpll_24m_p) = { "cpll", "xin24m" }; > +PNAME(gpll_cpll_p) = { "gpll", "cpll" }; > +PNAME(gpll_spll_p) = { "gpll", "spll" }; > +PNAME(gpll_cpll_aupll_p) = { "gpll", "cpll", "aupll" }; > +PNAME(gpll_cpll_24m_p) = { "gpll", "cpll", "xin24m" }; > +PNAME(gpll_cpll_24m_spll_p) = { "gpll", "cpll", "xin24m", "spll" }; > +PNAME(gpll_cpll_aupll_24m_p) = { "gpll", "cpll", "aupll", "xin24m" }; > +PNAME(gpll_cpll_aupll_spll_p) = { "gpll", "cpll", "aupll", "spll" }; > +PNAME(gpll_cpll_aupll_spll_lpll_p) = { "gpll", "cpll", "aupll", > "spll", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_bpll_p) = { "gpll", "cpll", "spll", "bpll_dummy" > }; > +PNAME(gpll_cpll_lpll_bpll_p) = { "gpll", "cpll", "lpll_dummy", > "bpll_dummy" }; > +PNAME(gpll_spll_cpll_bpll_lpll_p) = { "gpll", "spll", "cpll", > "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", > "aupll", "xin24m" }; > +PNAME(gpll_cpll_spll_aupll_bpll_p) = { "gpll", "cpll", "spll", > "aupll", "bpll_dummy" }; > +PNAME(gpll_cpll_spll_bpll_lpll_p) = { "gpll", "cpll", "spll", > "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_lpll_bpll_p) = { "gpll", "cpll", "spll", > "lpll_dummy", "bpll_dummy" }; > +PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", > "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_spll_aupll_bpll_lpll_p) = { "gpll", "spll", "aupll", > "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_spll_isppvtpll_bpll_lpll_p) = { "gpll", "spll", > "isp_pvtpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(gpll_cpll_spll_aupll_lpll_24m_p) = { "gpll", "cpll", "spll", > "aupll", "lpll_dummy", "xin24m" }; > +PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", > "vpll", "bpll_dummy", "lpll_dummy" }; > +PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", > "bpll_dummy" }; > +PNAME(mux_24m_ccipvtpll_gpll_lpll_p) = { "xin24m", "cci_pvtpll", > "gpll", "lpll" }; > +PNAME(mux_24m_spll_gpll_cpll_p) = {"xin24m", "spll", "gpll", "cpll" > }; > +PNAME(audio_frac_int_p) = { "xin24m", "clk_audio_frac_0", > "clk_audio_frac_1", "clk_audio_frac_2", > + "clk_audio_frac_3", "clk_audio_int_0", "clk_audio_int_1", > "clk_audio_int_2" }; > +PNAME(audio_frac_p) = { "clk_audio_frac_0", "clk_audio_frac_1", > "clk_audio_frac_2", "clk_audio_frac_3" }; > +PNAME(mux_100m_24m_p) = { "clk_cpll_div10", "xin24m" }; > +PNAME(mux_100m_50m_24m_p) = { "clk_cpll_div10", "clk_cpll_div20", > "xin24m" }; > +PNAME(mux_100m_24m_lclk0_p) = { "clk_cpll_div10", "xin24m", > "lclk_asrc_src_0" }; > +PNAME(mux_100m_24m_lclk1_p) = { "clk_cpll_div10", "xin24m", > "lclk_asrc_src_1" }; > +PNAME(mux_150m_100m_50m_24m_p) = { "clk_gpll_div8", > "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; > +PNAME(mux_200m_100m_50m_24m_p) = { "clk_gpll_div6", > "clk_cpll_div10", "clk_cpll_div20", "xin24m" }; > +PNAME(mux_400m_200m_100m_24m_p) = { "clk_gpll_div3", > "clk_gpll_div6", "clk_cpll_div10", "xin24m" }; > +PNAME(mux_500m_250m_100m_24m_p) = { "clk_cpll_div2", > "clk_cpll_div4", "clk_cpll_div10", "xin24m" }; > +PNAME(mux_600m_400m_300m_24m_p) = { "clk_gpll_div2", > "clk_gpll_div3", "clk_gpll_div4", "xin24m" }; > +PNAME(mux_350m_175m_116m_24m_p) = { "clk_spll_div2", > "clk_spll_div4", "clk_spll_div6", "xin24m" }; > +PNAME(mux_175m_116m_58m_24m_p) = { "clk_spll_div4", "clk_spll_div6", > "clk_spll_div12", "xin24m" }; > +PNAME(mux_116m_58m_24m_p) = { "clk_spll_div6", "clk_spll_div12", > "xin24m" }; > +PNAME(mclk_sai0_8ch_p) = { "mclk_sai0_8ch_src", "sai0_mclkin", > "sai1_mclkin" }; > +PNAME(mclk_sai1_8ch_p) = { "mclk_sai1_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai2_2ch_p) = { "mclk_sai2_2ch_src", "sai2_mclkin", > "sai1_mclkin" }; > +PNAME(mclk_sai3_2ch_p) = { "mclk_sai3_2ch_src", "sai3_mclkin", > "sai1_mclkin" }; > +PNAME(mclk_sai4_2ch_p) = { "mclk_sai4_2ch_src", "sai4_mclkin", > "sai1_mclkin" }; > +PNAME(mclk_sai5_8ch_p) = { "mclk_sai5_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai6_8ch_p) = { "mclk_sai6_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai7_8ch_p) = { "mclk_sai7_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai8_8ch_p) = { "mclk_sai8_8ch_src", "sai1_mclkin" }; > +PNAME(mclk_sai9_8ch_p) = { "mclk_sai9_8ch_src", "sai1_mclkin" }; > +PNAME(uart1_p) = { "clk_uart1_src_top", "xin24m" }; > +PNAME(pdm0_p) = { "clk_pdm0_src_top", "xin24m" }; > +PNAME(mclk_pdm0_p) = { "mclk_pdm0_src_top", "xin24m" }; > +PNAME(clk_gmac1_ptp_ref_src_p) = { "gpll", "cpll", > "gmac1_ptp_refclk_in" }; > +PNAME(clk_gmac0_ptp_ref_src_p) = { "gpll", "cpll", > "gmac0_ptp_refclk_in" }; > +PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy", > + "dclk_ebc_frac", "xin24m" }; > +PNAME(dclk_vp0_p) = { "dclk_vp0_src", "clk_hdmiphy_pixel0" }; > +PNAME(dclk_vp1_p) = { "dclk_vp1_src", "clk_hdmiphy_pixel0" }; > +PNAME(dclk_vp2_p) = { "dclk_vp2_src", "clk_hdmiphy_pixel0" }; > +PNAME(clk_uart_p) = { "gpll", "cpll", "aupll", "xin24m", > "clk_uart_frac_0", > + "clk_uart_frac_1", "clk_uart_frac_2"}; > +PNAME(clk_freq_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", > "sai2_mclkin", > + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_freq"}; > +PNAME(clk_counter_pwm1_p) = { "sai0_mclkin", "sai1_mclkin", > "sai2_mclkin", > + "sai3_mclkin", "sai4_mclkin", "sai_sclkin_counter"}; > +PNAME(sai_sclkin_freq_p) = { "sai0_sclk_in", "sai1_sclk_in", > "sai2_sclk_in", > + "sai3_sclk_in", "sai4_sclk_in"}; > +PNAME(clk_ref_pcie0_phy_p) = { "clk_pcie_100m_src", > "clk_pcie_100m_nduty_src", > + "xin24m"}; > +PNAME(hclk_vi_root_p) = { "clk_gpll_div6", "clk_cpll_div10", > + "aclk_vi_root_inter", "xin24m"}; > +PNAME(clk_ref_osc_mphy_p) = { "xin24m", "clk_gpio_mphy_i", > "clk_ref_mphy_26m"}; > +PNAME(mux_pmu200m_pmu100m_pmu50m_24m_p) = { "clk_200m_pmu_src", > "clk_100m_pmu_src", > + "clk_50m_pmu_src", "xin24m" }; > +PNAME(mux_pmu100m_pmu50m_24m_p) = { "clk_100m_pmu_src", > "clk_50m_pmu_src", "xin24m" }; > +PNAME(mux_pmu100m_24m_32k_p) = { "clk_100m_pmu_src", "xin24m", > "xin_osc0_div" }; > +PNAME(clk_phy_ref_src_p) = { "xin24m", "clk_pmuphy_ref_src" }; > +PNAME(clk_usbphy_ref_src_p) = { "usbphy0_24m", "usbphy1_24m" }; > +PNAME(clk_cpll_ref_src_p) = { "xin24m", "clk_usbphy_ref_src" }; > +PNAME(clk_aupll_ref_src_p) = { "xin24m", "clk_aupll_ref_io" }; > + > +static struct rockchip_pll_clock rk3576_pll_clks[] __initdata = { > + [bpll] = PLL(pll_rk3588_core, PLL_BPLL, "bpll", mux_pll_p, > + 0, RK3576_PLL_CON(0), > + RK3576_BPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), > + [lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p, > + 0, RK3576_LPLL_CON(16), > + RK3576_LPLL_MODE_CON0, 0, 15, 0, rk3576_pll_rates), > + [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p, > + 0, RK3576_PLL_CON(88), > + RK3576_MODE_CON0, 4, 15, 0, rk3576_pll_rates), > + [aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p, > + 0, RK3576_PLL_CON(96), > + RK3576_MODE_CON0, 6, 15, 0, rk3576_pll_rates), > + [cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PLL_CON(104), > + RK3576_MODE_CON0, 8, 15, 0, rk3576_pll_rates), > + [gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PLL_CON(112), > + RK3576_MODE_CON0, 2, 15, 0, rk3576_pll_rates), > + [ppll] = PLL(pll_rk3588_ddr, PLL_PPLL, "ppll", mux_pll_p, > + CLK_IGNORE_UNUSED, RK3576_PMU_PLL_CON(128), > + RK3576_MODE_CON0, 10, 15, 0, rk3576_ppll_rates), > +}; > + > +static struct rockchip_clk_branch rk3576_clk_branches[] __initdata = { > + /* > + * CRU Clock-Architecture > + */ > + /* fixed */ > + FACTOR(0, "xin12m", "xin24m", 0, 1, 2), > + > + COMPOSITE_FRAC(XIN_OSC0_DIV, "xin_osc0_div", "xin24m", > CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(21), 0, > + RK3576_PMU_CLKGATE_CON(7), 11, GFLAGS), > + > + FACTOR(0, "clk_spll_div12", "spll", 0, 1, 12), > + FACTOR(0, "clk_spll_div6", "spll", 0, 1, 6), > + FACTOR(0, "clk_spll_div4", "spll", 0, 1, 4), > + FACTOR(0, "lpll_div2", "lpll", 0, 1, 2), > + FACTOR(0, "bpll_div4", "bpll", 0, 1, 4), > + > + /* top */ > + COMPOSITE(CLK_CPLL_DIV20, "clk_cpll_div20", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 0, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV10, "clk_cpll_div10", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV8, "clk_gpll_div8", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 2, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV6, "clk_gpll_div6", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 3, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV4, "clk_cpll_div4", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 4, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV4, "clk_gpll_div4", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 5, GFLAGS), > + COMPOSITE(CLK_SPLL_DIV2, "clk_spll_div2", gpll_cpll_spll_bpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(3), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 6, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV3, "clk_gpll_div3", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(3), 12, 1, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE(CLK_CPLL_DIV2, "clk_cpll_div2", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 9, GFLAGS), > + COMPOSITE(CLK_GPLL_DIV2, "clk_gpll_div2", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 10, GFLAGS), > + COMPOSITE(CLK_SPLL_DIV1, "clk_spll_div1", > gpll_cpll_spll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(6), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(0), 12, GFLAGS), > + COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(8), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(1), 1, GFLAGS), > + COMPOSITE(ACLK_TOP, "aclk_top", gpll_cpll_aupll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(9), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 3, GFLAGS), > + COMPOSITE(ACLK_TOP_MID, "aclk_top_mid", gpll_cpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(10), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 6, GFLAGS), > + COMPOSITE(ACLK_SECURE_HIGH, "aclk_secure_high", > gpll_spll_aupll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(10), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(1), 7, GFLAGS), > + COMPOSITE_NODIV(HCLK_TOP, "hclk_top", mux_200m_100m_50m_24m_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(1), 14, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO0VOP_CHANNEL, "hclk_vo0vop_channel", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(2), 0, GFLAGS), > + COMPOSITE(ACLK_VO0VOP_CHANNEL, "aclk_vo0vop_channel", > gpll_cpll_lpll_bpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(19), 12, 2, MFLAGS, 8, 4, DFLAGS, > + RK3576_CLKGATE_CON(2), 1, GFLAGS), > + MUX(CLK_AUDIO_FRAC_0_SRC, "clk_audio_frac_0_src", > gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(13), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_0, "clk_audio_frac_0", > "clk_audio_frac_0_src", 0, > + RK3576_CLKSEL_CON(12), 0, > + RK3576_CLKGATE_CON(1), 10, GFLAGS), > + MUX(CLK_AUDIO_FRAC_1_SRC, "clk_audio_frac_1_src", > gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(15), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_1, "clk_audio_frac_1", > "clk_audio_frac_1_src", 0, > + RK3576_CLKSEL_CON(14), 0, > + RK3576_CLKGATE_CON(1), 11, GFLAGS), > + MUX(CLK_AUDIO_FRAC_2_SRC, "clk_audio_frac_2_src", > gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(17), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_2, "clk_audio_frac_2", > "clk_audio_frac_2_src", 0, > + RK3576_CLKSEL_CON(16), 0, > + RK3576_CLKGATE_CON(1), 12, GFLAGS), > + MUX(CLK_AUDIO_FRAC_3_SRC, "clk_audio_frac_3_src", > gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(19), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_AUDIO_FRAC_3, "clk_audio_frac_3", > "clk_audio_frac_3_src", 0, > + RK3576_CLKSEL_CON(18), 0, > + RK3576_CLKGATE_CON(1), 13, GFLAGS), > + MUX(0, "clk_uart_frac_0_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(22), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_0, "clk_uart_frac_0", > "clk_uart_frac_0_src", 0, > + RK3576_CLKSEL_CON(21), 0, > + RK3576_CLKGATE_CON(2), 5, GFLAGS), > + MUX(0, "clk_uart_frac_1_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(24), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_1, "clk_uart_frac_1", > "clk_uart_frac_1_src", 0, > + RK3576_CLKSEL_CON(23), 0, > + RK3576_CLKGATE_CON(2), 6, GFLAGS), > + MUX(0, "clk_uart_frac_2_src", gpll_cpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(26), 0, 2, MFLAGS), > + COMPOSITE_FRAC(CLK_UART_FRAC_2, "clk_uart_frac_2", > "clk_uart_frac_2_src", 0, > + RK3576_CLKSEL_CON(25), 0, > + RK3576_CLKGATE_CON(2), 7, GFLAGS), > + COMPOSITE(CLK_UART1_SRC_TOP, "clk_uart1_src_top", clk_uart_p, 0, > + RK3576_CLKSEL_CON(27), 13, 3, MFLAGS, 5, 8, DFLAGS, > + RK3576_CLKGATE_CON(2), 13, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_0, "clk_audio_int_0", "gpll", 0, > + RK3576_CLKSEL_CON(28), 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(2), 14, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_1, "clk_audio_int_1", "cpll", 0, > + RK3576_CLKSEL_CON(28), 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(2), 15, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUDIO_INT_2, "clk_audio_int_2", "aupll", 0, > + RK3576_CLKSEL_CON(28), 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 0, GFLAGS), > + COMPOSITE(CLK_PDM0_SRC_TOP, "clk_pdm0_src_top", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(29), 9, 3, MFLAGS, 0, 9, DFLAGS, > + RK3576_CLKGATE_CON(3), 2, GFLAGS), > + COMPOSITE_NOMUX(CLK_GMAC0_125M_SRC, "clk_gmac0_125m_src", "cpll", 0, > + RK3576_CLKSEL_CON(30), 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 6, GFLAGS), > + COMPOSITE_NOMUX(CLK_GMAC1_125M_SRC, "clk_gmac1_125m_src", "cpll", 0, > + RK3576_CLKSEL_CON(31), 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 7, GFLAGS), > + COMPOSITE(LCLK_ASRC_SRC_0, "lclk_asrc_src_0", audio_frac_p, 0, > + RK3576_CLKSEL_CON(31), 10, 2, MFLAGS, 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 10, GFLAGS), > + COMPOSITE(LCLK_ASRC_SRC_1, "lclk_asrc_src_1", audio_frac_p, 0, > + RK3576_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(3), 11, GFLAGS), > + COMPOSITE(REF_CLK0_OUT_PLL, "ref_clk0_out_pll", > gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(33), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 1, GFLAGS), > + COMPOSITE(REF_CLK1_OUT_PLL, "ref_clk1_out_pll", > gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(34), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 2, GFLAGS), > + COMPOSITE(REF_CLK2_OUT_PLL, "ref_clk2_out_pll", > gpll_cpll_spll_aupll_lpll_24m_p, 0, > + RK3576_CLKSEL_CON(35), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(4), 3, GFLAGS), > + COMPOSITE(REFCLKO25M_GMAC0_OUT, "refclko25m_gmac0_out", gpll_cpll_p, > 0, > + RK3576_CLKSEL_CON(36), 7, 1, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(5), 10, GFLAGS), > + COMPOSITE(REFCLKO25M_GMAC1_OUT, "refclko25m_gmac1_out", gpll_cpll_p, > 0, > + RK3576_CLKSEL_CON(36), 15, 1, MFLAGS, 8, 7, DFLAGS, > + RK3576_CLKGATE_CON(5), 11, GFLAGS), > + COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0, > + RK3576_CLKSEL_CON(37), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(5), 12, GFLAGS), > + GATE(CLK_GMAC0_RMII_CRU, "clk_gmac0_rmii_cru", "clk_cpll_div20", 0, > + RK3576_CLKGATE_CON(5), 13, GFLAGS), > + GATE(CLK_GMAC1_RMII_CRU, "clk_gmac1_rmii_cru", "clk_cpll_div20", 0, > + RK3576_CLKGATE_CON(5), 14, GFLAGS), > + GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0, > + RK3576_CLKGATE_CON(5), 15, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M0, "clk_mipi_cameraout_m0", > mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(38), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 3, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M1, "clk_mipi_cameraout_m1", > mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(39), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 4, GFLAGS), > + COMPOSITE(CLK_MIPI_CAMERAOUT_M2, "clk_mipi_cameraout_m2", > mux_24m_spll_gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(40), 8, 2, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(6), 5, GFLAGS), > + COMPOSITE(MCLK_PDM0_SRC_TOP, "mclk_pdm0_src_top", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(41), 7, 3, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(6), 8, GFLAGS), > + > + /* bus */ > + COMPOSITE_NODIV(HCLK_BUS_ROOT, "hclk_bus_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(11), 0, GFLAGS), > + COMPOSITE_NODIV(PCLK_BUS_ROOT, "pclk_bus_root", mux_100m_50m_24m_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(11), 1, GFLAGS), > + COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(55), 9, 1, MFLAGS, 4, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 2, GFLAGS), > + GATE(HCLK_CAN0, "hclk_can0", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(11), 6, GFLAGS), > + COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(56), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 7, GFLAGS), > + GATE(HCLK_CAN1, "hclk_can1", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(11), 8, GFLAGS), > + COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(56), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(11), 9, GFLAGS), > + GATE(CLK_KEY_SHIFT, "clk_key_shift", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(11), 15, GFLAGS), > + GATE(PCLK_I2C1, "pclk_i2c1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 0, GFLAGS), > + GATE(PCLK_I2C2, "pclk_i2c2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 1, GFLAGS), > + GATE(PCLK_I2C3, "pclk_i2c3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 2, GFLAGS), > + GATE(PCLK_I2C4, "pclk_i2c4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 3, GFLAGS), > + GATE(PCLK_I2C5, "pclk_i2c5", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 4, GFLAGS), > + GATE(PCLK_I2C6, "pclk_i2c6", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 5, GFLAGS), > + GATE(PCLK_I2C7, "pclk_i2c7", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 6, GFLAGS), > + GATE(PCLK_I2C8, "pclk_i2c8", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 7, GFLAGS), > + GATE(PCLK_I2C9, "pclk_i2c9", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 8, GFLAGS), > + GATE(PCLK_WDT_BUSMCU, "pclk_wdt_busmcu", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(12), 9, GFLAGS), > + GATE(TCLK_WDT_BUSMCU, "tclk_wdt_busmcu", "xin24m", 0, > + RK3576_CLKGATE_CON(12), 10, GFLAGS), > + GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(12), 11, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 12, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 13, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 4, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 14, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(12), 15, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 0, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(57), 14, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 3, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C9, "clk_i2c9", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(58), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(13), 4, GFLAGS), > + GATE(PCLK_SARADC, "pclk_saradc", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 6, GFLAGS), > + COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0, > + RK3576_CLKSEL_CON(58), 12, 1, MFLAGS, 4, 8, DFLAGS, > + RK3576_CLKGATE_CON(13), 7, GFLAGS), > + GATE(PCLK_TSADC, "pclk_tsadc", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 8, GFLAGS), > + COMPOSITE_NOMUX(CLK_TSADC, "clk_tsadc", "xin24m", 0, > + RK3576_CLKSEL_CON(59), 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(13), 9, GFLAGS), > + GATE(PCLK_UART0, "pclk_uart0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 10, GFLAGS), > + GATE(PCLK_UART2, "pclk_uart2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 11, GFLAGS), > + GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 12, GFLAGS), > + GATE(PCLK_UART4, "pclk_uart4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 13, GFLAGS), > + GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 14, GFLAGS), > + GATE(PCLK_UART6, "pclk_uart6", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(13), 15, GFLAGS), > + GATE(PCLK_UART7, "pclk_uart7", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 0, GFLAGS), > + GATE(PCLK_UART8, "pclk_uart8", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 1, GFLAGS), > + GATE(PCLK_UART9, "pclk_uart9", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 2, GFLAGS), > + GATE(PCLK_UART10, "pclk_uart10", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 3, GFLAGS), > + GATE(PCLK_UART11, "pclk_uart11", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(14), 4, GFLAGS), > + COMPOSITE(SCLK_UART0, "sclk_uart0", clk_uart_p, 0, > + RK3576_CLKSEL_CON(60), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 5, GFLAGS), > + COMPOSITE(SCLK_UART2, "sclk_uart2", clk_uart_p, 0, > + RK3576_CLKSEL_CON(61), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 6, GFLAGS), > + COMPOSITE(SCLK_UART3, "sclk_uart3", clk_uart_p, 0, > + RK3576_CLKSEL_CON(62), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 9, GFLAGS), > + COMPOSITE(SCLK_UART4, "sclk_uart4", clk_uart_p, 0, > + RK3576_CLKSEL_CON(63), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 12, GFLAGS), > + COMPOSITE(SCLK_UART5, "sclk_uart5", clk_uart_p, 0, > + RK3576_CLKSEL_CON(64), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(14), 15, GFLAGS), > + COMPOSITE(SCLK_UART6, "sclk_uart6", clk_uart_p, 0, > + RK3576_CLKSEL_CON(65), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 2, GFLAGS), > + COMPOSITE(SCLK_UART7, "sclk_uart7", clk_uart_p, 0, > + RK3576_CLKSEL_CON(66), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 5, GFLAGS), > + COMPOSITE(SCLK_UART8, "sclk_uart8", clk_uart_p, 0, > + RK3576_CLKSEL_CON(67), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 8, GFLAGS), > + COMPOSITE(SCLK_UART9, "sclk_uart9", clk_uart_p, 0, > + RK3576_CLKSEL_CON(68), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 9, GFLAGS), > + COMPOSITE(SCLK_UART10, "sclk_uart10", clk_uart_p, 0, > + RK3576_CLKSEL_CON(69), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 10, GFLAGS), > + COMPOSITE(SCLK_UART11, "sclk_uart11", clk_uart_p, 0, > + RK3576_CLKSEL_CON(70), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(15), 11, GFLAGS), > + GATE(PCLK_SPI0, "pclk_spi0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 13, GFLAGS), > + GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 14, GFLAGS), > + GATE(PCLK_SPI2, "pclk_spi2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(15), 15, GFLAGS), > + GATE(PCLK_SPI3, "pclk_spi3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 0, GFLAGS), > + GATE(PCLK_SPI4, "pclk_spi4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(70), 13, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 3, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 2, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 4, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 5, GFLAGS), > + COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 6, GFLAGS), > + GATE(PCLK_WDT0, "pclk_wdt0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 7, GFLAGS), > + GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0, > + RK3576_CLKGATE_CON(16), 8, GFLAGS), > + GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(16), 10, GFLAGS), > + COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(71), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(16), 11, GFLAGS), > + GATE(CLK_OSC_PWM1, "clk_osc_pwm1", "xin24m", 0, > + RK3576_CLKGATE_CON(16), 13, GFLAGS), > + GATE(CLK_RC_PWM1, "clk_rc_pwm1", "clk_pvtm_clkout", 0, > + RK3576_CLKGATE_CON(16), 15, GFLAGS), > + GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 3, GFLAGS), > + GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_TIMER0_ROOT, "clk_timer0_root", mux_100m_24m_p, > 0, > + RK3576_CLKSEL_CON(71), 14, 1, MFLAGS, > + RK3576_CLKGATE_CON(17), 5, GFLAGS), > + GATE(CLK_TIMER0, "clk_timer0", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 6, GFLAGS), > + GATE(CLK_TIMER1, "clk_timer1", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 7, GFLAGS), > + GATE(CLK_TIMER2, "clk_timer2", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 8, GFLAGS), > + GATE(CLK_TIMER3, "clk_timer3", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 9, GFLAGS), > + GATE(CLK_TIMER4, "clk_timer4", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 10, GFLAGS), > + GATE(CLK_TIMER5, "clk_timer5", "clk_timer0_root", 0, > + RK3576_CLKGATE_CON(17), 11, GFLAGS), > + GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 13, GFLAGS), > + GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(17), 15, GFLAGS), > + GATE(DBCLK_GPIO1, "dbclk_gpio1", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 0, GFLAGS), > + GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 1, GFLAGS), > + GATE(DBCLK_GPIO2, "dbclk_gpio2", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 2, GFLAGS), > + GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 3, GFLAGS), > + GATE(DBCLK_GPIO3, "dbclk_gpio3", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 4, GFLAGS), > + GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 5, GFLAGS), > + GATE(DBCLK_GPIO4, "dbclk_gpio4", "xin24m", 0, > + RK3576_CLKGATE_CON(18), 6, GFLAGS), > + GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 7, GFLAGS), > + GATE(PCLK_DECOM, "pclk_decom", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(18), 8, GFLAGS), > + COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0, > + RK3576_CLKSEL_CON(72), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 9, GFLAGS), > + COMPOSITE_NODIV(CLK_TIMER1_ROOT, "clk_timer1_root", mux_100m_24m_p, > 0, > + RK3576_CLKSEL_CON(72), 6, 1, MFLAGS, > + RK3576_CLKGATE_CON(18), 10, GFLAGS), > + GATE(CLK_TIMER6, "clk_timer6", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 11, GFLAGS), > + COMPOSITE(CLK_TIMER7, "clk_timer7", mux_100m_24m_lclk0_p, 0, > + RK3576_CLKSEL_CON(72), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 12, GFLAGS), > + COMPOSITE(CLK_TIMER8, "clk_timer8", mux_100m_24m_lclk1_p, 0, > + RK3576_CLKSEL_CON(73), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(18), 13, GFLAGS), > + GATE(CLK_TIMER9, "clk_timer9", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 14, GFLAGS), > + GATE(CLK_TIMER10, "clk_timer10", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(18), 15, GFLAGS), > + GATE(CLK_TIMER11, "clk_timer11", "clk_timer1_root", 0, > + RK3576_CLKGATE_CON(19), 0, GFLAGS), > + GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 1, GFLAGS), > + GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 2, GFLAGS), > + GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 3, GFLAGS), > + GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 4, GFLAGS), > + GATE(HCLK_I3C0, "hclk_i3c0", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 7, GFLAGS), > + GATE(HCLK_I3C1, "hclk_i3c1", "hclk_bus_root", 0, > + RK3576_CLKGATE_CON(19), 9, GFLAGS), > + COMPOSITE_NODIV(HCLK_BUS_CM0_ROOT, "hclk_bus_cm0_root", > mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(73), 13, 2, MFLAGS, > + RK3576_CLKGATE_CON(19), 10, GFLAGS), > + GATE(FCLK_BUS_CM0_CORE, "fclk_bus_cm0_core", "hclk_bus_cm0_root", 0, > + RK3576_CLKGATE_CON(19), 12, GFLAGS), > + COMPOSITE(CLK_BUS_CM0_RTC, "clk_bus_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(74), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(19), 14, GFLAGS), > + GATE(PCLK_PMU2, "pclk_pmu2", "pclk_bus_root", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(19), 15, GFLAGS), > + GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(20), 4, GFLAGS), > + COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(74), 6, 2, MFLAGS, > + RK3576_CLKGATE_CON(20), 5, GFLAGS), > + GATE(CLK_OSC_PWM2, "clk_osc_pwm2", "xin24m", 0, > + RK3576_CLKGATE_CON(20), 7, GFLAGS), > + GATE(CLK_RC_PWM2, "clk_rc_pwm2", "clk_pvtm_clkout", 0, > + RK3576_CLKGATE_CON(20), 6, GFLAGS), > + COMPOSITE_NODIV(CLK_FREQ_PWM1, "clk_freq_pwm1", clk_freq_pwm1_p, 0, > + RK3576_CLKSEL_CON(74), 8, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 8, GFLAGS), > + COMPOSITE_NODIV(CLK_COUNTER_PWM1, "clk_counter_pwm1", > clk_counter_pwm1_p, 0, > + RK3576_CLKSEL_CON(74), 11, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 9, GFLAGS), > + COMPOSITE_NODIV(SAI_SCLKIN_FREQ, "sai_sclkin_freq", > sai_sclkin_freq_p, 0, > + RK3576_CLKSEL_CON(75), 0, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 10, GFLAGS), > + COMPOSITE_NODIV(SAI_SCLKIN_COUNTER, "sai_sclkin_counter", > sai_sclkin_freq_p, 0, > + RK3576_CLKSEL_CON(75), 3, 3, MFLAGS, > + RK3576_CLKGATE_CON(20), 11, GFLAGS), > + COMPOSITE(CLK_I3C0, "clk_i3c0", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(78), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(20), 12, GFLAGS), > + COMPOSITE(CLK_I3C1, "clk_i3c1", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(78), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(20), 13, GFLAGS), > + GATE(PCLK_CSIDPHY1, "pclk_csidphy1", "pclk_bus_root", 0, > + RK3576_CLKGATE_CON(40), 2, GFLAGS), > + > + /* cci */ > + COMPOSITE(PCLK_CCI_ROOT, "pclk_cci_root", > mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CCI_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CCI_CLKGATE_CON(1), 10, GFLAGS), > + COMPOSITE(ACLK_CCI_ROOT, "aclk_cci_root", > mux_24m_ccipvtpll_gpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CCI_CLKSEL_CON(4), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CCI_CLKGATE_CON(1), 11, GFLAGS), > + > + /* center */ > + COMPOSITE_DIV_OFFSET(ACLK_CENTER_ROOT, "aclk_center_root", > gpll_cpll_spll_aupll_bpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 5, 3, MFLAGS, > + RK3576_CLKSEL_CON(167), 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(72), 0, GFLAGS), > + COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", > mux_500m_250m_100m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(168), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(72), 3, GFLAGS), > + GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", > CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 5, GFLAGS), > + GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", > CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 6, GFLAGS), > + GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", > CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 10, GFLAGS), > + GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", > CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(72), 11, GFLAGS), > + > + /* ddr */ > + COMPOSITE(PCLK_DDR_ROOT, "pclk_ddr_root", gpll_cpll_24m_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(76), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(21), 0, GFLAGS), > + GATE(PCLK_DDR_MON_CH0, "pclk_ddr_mon_ch0", "pclk_ddr_root", > CLK_IGNORE_UNUSED, > + RK3576_CLKGATE_CON(21), 1, GFLAGS), > + COMPOSITE(HCLK_DDR_ROOT, "hclk_ddr_root", gpll_cpll_p, > CLK_IGNORE_UNUSED, > + RK3576_CLKSEL_CON(77), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(22), 11, GFLAGS), > + GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_ddr_root", > CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(22), 15, GFLAGS), > + COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", > mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(77), 6, 1, MFLAGS, > + RK3576_CLKGATE_CON(23), 3, GFLAGS), > + GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0, > + RK3576_CLKGATE_CON(23), 4, GFLAGS), > + GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0, > + RK3576_CLKGATE_CON(23), 5, GFLAGS), > + GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0, > + RK3576_CLKGATE_CON(23), 6, GFLAGS), > + GATE(PCLK_WDT, "pclk_wdt", "pclk_ddr_root", 0, > + RK3576_CLKGATE_CON(23), 7, GFLAGS), > + GATE(PCLK_TIMER, "pclk_timer", "pclk_ddr_root", 0, > + RK3576_CLKGATE_CON(23), 8, GFLAGS), > + COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(77), 12, 1, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(23), 10, GFLAGS), > + > + /* gpu */ > + COMPOSITE(CLK_GPU_SRC_PRE, "clk_gpu_src_pre", > gpll_cpll_aupll_spll_lpll_p, 0, > + RK3576_CLKSEL_CON(165), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(69), 1, GFLAGS), > + GATE(CLK_GPU, "clk_gpu", "clk_gpu_src_pre", 0, > + RK3576_CLKGATE_CON(69), 3, GFLAGS), > + COMPOSITE_NODIV(PCLK_GPU_ROOT, "pclk_gpu_root", mux_100m_50m_24m_p, > 0, > + RK3576_CLKSEL_CON(166), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(69), 8, GFLAGS), > + > + /* npu */ > + COMPOSITE_NODIV(HCLK_RKNN_ROOT, "hclk_rknn_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(86), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(31), 4, GFLAGS), > + COMPOSITE(CLK_RKNN_DSU0, "clk_rknn_dsu0", gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(86), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(31), 5, GFLAGS), > + GATE(ACLK_RKNN0, "aclk_rknn0", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(28), 9, GFLAGS), > + GATE(ACLK_RKNN1, "aclk_rknn1", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(29), 0, GFLAGS), > + COMPOSITE_NODIV(PCLK_NPUTOP_ROOT, "pclk_nputop_root", > mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(31), 8, GFLAGS), > + GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_nputop_root", 0, > + RK3576_CLKGATE_CON(31), 10, GFLAGS), > + COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", > mux_100m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 2, 1, MFLAGS, > + RK3576_CLKGATE_CON(31), 11, GFLAGS), > + GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0, > + RK3576_CLKGATE_CON(31), 12, GFLAGS), > + GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0, > + RK3576_CLKGATE_CON(31), 13, GFLAGS), > + GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_nputop_root", 0, > + RK3576_CLKGATE_CON(31), 14, GFLAGS), > + GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0, > + RK3576_CLKGATE_CON(31), 15, GFLAGS), > + GATE(ACLK_RKNN_CBUF, "aclk_rknn_cbuf", "clk_rknn_dsu0", 0, > + RK3576_CLKGATE_CON(32), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", > mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(87), 3, 2, MFLAGS, > + RK3576_CLKGATE_CON(32), 5, GFLAGS), > + GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0, > + RK3576_CLKGATE_CON(32), 7, GFLAGS), > + COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_CLKSEL_CON(87), 10, 1, MFLAGS, 5, 5, DFLAGS, > + RK3576_CLKGATE_CON(32), 9, GFLAGS), > + GATE(HCLK_RKNN_CBUF, "hclk_rknn_cbuf", "hclk_rknn_root", 0, > + RK3576_CLKGATE_CON(32), 12, GFLAGS), > + > + /* nvm */ > + COMPOSITE_NODIV(HCLK_NVM_ROOT, "hclk_nvm_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(88), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(33), 0, GFLAGS), > + COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(88), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(33), 1, GFLAGS), > + COMPOSITE(SCLK_FSPI_X2, "sclk_fspi_x2", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(89), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(33), 6, GFLAGS), > + GATE(HCLK_FSPI, "hclk_fspi", "hclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 7, GFLAGS), > + COMPOSITE(CCLK_SRC_EMMC, "cclk_src_emmc", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(89), 14, 2, MFLAGS, 8, 6, DFLAGS, > + RK3576_CLKGATE_CON(33), 8, GFLAGS), > + GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 9, GFLAGS), > + GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0, > + RK3576_CLKGATE_CON(33), 10, GFLAGS), > + COMPOSITE_NODIV(BCLK_EMMC, "bclk_emmc", mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(90), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(33), 11, GFLAGS), > + GATE(TCLK_EMMC, "tclk_emmc", "xin24m", 0, > + RK3576_CLKGATE_CON(33), 12, GFLAGS), > + > + /* usb */ > + COMPOSITE(ACLK_UFS_ROOT, "aclk_ufs_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(115), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(47), 0, GFLAGS), > + COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(115), 11, 1, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(47), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_USB_ROOT, "pclk_usb_root", mux_100m_50m_24m_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(115), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(47), 2, GFLAGS), > + GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 5, GFLAGS), > + GATE(CLK_REF_USB3OTG0, "clk_ref_usb3otg0", "xin24m", 0, > + RK3576_CLKGATE_CON(47), 6, GFLAGS), > + GATE(CLK_SUSPEND_USB3OTG0, "clk_suspend_usb3otg0", "xin24m", 0, > + RK3576_CLKGATE_CON(47), 7, GFLAGS), > + GATE(ACLK_MMU2, "aclk_mmu2", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 12, GFLAGS), > + GATE(ACLK_SLV_MMU2, "aclk_slv_mmu2", "aclk_usb_root", 0, > + RK3576_CLKGATE_CON(47), 13, GFLAGS), > + GATE(ACLK_UFS_SYS, "aclk_ufs_sys", "aclk_ufs_root", 0, > + RK3576_CLKGATE_CON(47), 15, GFLAGS), > + > + /* vdec */ > + COMPOSITE_NODIV(HCLK_RKVDEC_ROOT, "hclk_rkvdec_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(110), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(45), 0, GFLAGS), > + COMPOSITE(ACLK_RKVDEC_ROOT, "aclk_rkvdec_root", > gpll_cpll_aupll_spll_p, 0, > + RK3576_CLKSEL_CON(110), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 1, GFLAGS), > + COMPOSITE(ACLK_RKVDEC_ROOT_BAK, "aclk_rkvdec_root_bak", > cpll_vpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(110), 14, 2, MFLAGS, 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 2, GFLAGS), > + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_root", 0, > + RK3576_CLKGATE_CON(45), 3, GFLAGS), > + COMPOSITE(CLK_RKVDEC_HEVC_CA, "clk_rkvdec_hevc_ca", > gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(111), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(45), 8, GFLAGS), > + GATE(CLK_RKVDEC_CORE, "clk_rkvdec_core", "aclk_rkvdec_root", 0, > + RK3576_CLKGATE_CON(45), 9, GFLAGS), > + > + /* venc */ > + COMPOSITE_NODIV(HCLK_VEPU0_ROOT, "hclk_vepu0_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(124), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(51), 0, GFLAGS), > + COMPOSITE(ACLK_VEPU0_ROOT, "aclk_vepu0_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(51), 1, GFLAGS), > + COMPOSITE(CLK_VEPU0_CORE, "clk_vepu0_core", > gpll_cpll_spll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(124), 13, 3, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(51), 6, GFLAGS), > + GATE(HCLK_VEPU0, "hclk_vepu0", "hclk_vepu0_root", 0, > + RK3576_CLKGATE_CON(51), 4, GFLAGS), > + GATE(ACLK_VEPU0, "aclk_vepu0", "aclk_vepu0_root", 0, > + RK3576_CLKGATE_CON(51), 5, GFLAGS), > + > + /* vi */ > + COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", > gpll_spll_isppvtpll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(128), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 0, GFLAGS), > + COMPOSITE_NOMUX(ACLK_VI_ROOT_INTER, "aclk_vi_root_inter", > "aclk_vi_root", 0, > + RK3576_CLKSEL_CON(130), 10, 3, DFLAGS, > + RK3576_CLKGATE_CON(54), 13, GFLAGS), > + COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", hclk_vi_root_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(128), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(53), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(128), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(53), 2, GFLAGS), > + COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(129), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 6, GFLAGS), > + GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 7, GFLAGS), > + GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 8, GFLAGS), > + COMPOSITE(CLK_ISP_CORE, "clk_isp_core", > gpll_spll_isppvtpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(129), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(53), 9, GFLAGS), > + GATE(CLK_ISP_CORE_MARVIN, "clk_isp_core_marvin", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(53), 10, GFLAGS), > + GATE(CLK_ISP_CORE_VICAP, "clk_isp_core_vicap", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(53), 11, GFLAGS), > + GATE(ACLK_ISP, "aclk_isp", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 12, GFLAGS), > + GATE(HCLK_ISP, "hclk_isp", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 13, GFLAGS), > + GATE(ACLK_VPSS, "aclk_vpss", "aclk_vi_root", 0, > + RK3576_CLKGATE_CON(53), 15, GFLAGS), > + GATE(HCLK_VPSS, "hclk_vpss", "hclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 0, GFLAGS), > + GATE(CLK_CORE_VPSS, "clk_core_vpss", "clk_isp_core", 0, > + RK3576_CLKGATE_CON(54), 1, GFLAGS), > + GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 4, GFLAGS), > + GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 5, GFLAGS), > + GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 6, GFLAGS), > + GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 7, GFLAGS), > + GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0, > + RK3576_CLKGATE_CON(54), 8, GFLAGS), > + COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", > mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(130), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(54), 10, GFLAGS), > + GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0, > + RK3576_CLKGATE_CON(54), 11, GFLAGS), > + COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", > gpll_cpll_aupll_spll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(144), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(61), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(144), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(61), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, > 0, > + RK3576_CLKSEL_CON(144), 12, 2, MFLAGS, > + RK3576_CLKGATE_CON(61), 3, GFLAGS), > + GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0, > + RK3576_CLKGATE_CON(61), 8, GFLAGS), > + GATE(ACLK_VOP, "aclk_vop", "aclk_vop_root", 0, > + RK3576_CLKGATE_CON(61), 9, GFLAGS), > + COMPOSITE(DCLK_VP0_SRC, "dclk_vp0_src", gpll_cpll_vpll_bpll_lpll_p, > CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(145), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 10, GFLAGS), > + COMPOSITE(DCLK_VP1_SRC, "dclk_vp1_src", gpll_cpll_vpll_bpll_lpll_p, > CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(146), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 11, GFLAGS), > + COMPOSITE(DCLK_VP2_SRC, "dclk_vp2_src", gpll_cpll_vpll_bpll_lpll_p, > CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(61), 12, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP0, "dclk_vp0", dclk_vp0_p, > CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(61), 13, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP1, "dclk_vp1", dclk_vp1_p, > CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 12, 1, MFLAGS, > + RK3576_CLKGATE_CON(62), 0, GFLAGS), > + COMPOSITE_NODIV(DCLK_VP2, "dclk_vp2", dclk_vp2_p, > CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(147), 13, 1, MFLAGS, > + RK3576_CLKGATE_CON(62), 1, GFLAGS), > + > + /* vo0 */ > + COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(149), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(63), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(149), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(63), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", > mux_150m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(149), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(63), 3, GFLAGS), > + GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 12, GFLAGS), > + GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 13, GFLAGS), > + GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(63), 14, GFLAGS), > + GATE(CLK_TRNG0_SKP, "clk_trng0_skp", "aclk_hdcp0", 0, > + RK3576_CLKGATE_CON(64), 4, GFLAGS), > + GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 5, GFLAGS), > + COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", > gpll_cpll_spll_vpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(151), 7, 3, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(64), 6, GFLAGS), > + GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 7, GFLAGS), > + COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(151), 15, 1, MFLAGS, 10, 5, DFLAGS, > + RK3576_CLKGATE_CON(64), 8, GFLAGS), > + GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 9, GFLAGS), > + GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo0_root", 0, > + RK3576_CLKGATE_CON(64), 13, GFLAGS), > + GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0, > + RK3576_CLKGATE_CON(64), 14, GFLAGS), > + COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(152), 1, 2, MFLAGS, > + RK3576_CLKGATE_CON(64), 15, GFLAGS), > + COMPOSITE(MCLK_SAI5_8CH_SRC, "mclk_sai5_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(154), 10, 3, MFLAGS, 2, 8, DFLAGS, > + RK3576_CLKGATE_CON(65), 3, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI5_8CH, "mclk_sai5_8ch", mclk_sai5_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(154), 13, 1, MFLAGS, > + RK3576_CLKGATE_CON(65), 4, GFLAGS), > + GATE(HCLK_SAI5_8CH, "hclk_sai5_8ch", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 5, GFLAGS), > + COMPOSITE(MCLK_SAI6_8CH_SRC, "mclk_sai6_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(155), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(65), 7, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI6_8CH, "mclk_sai6_8ch", mclk_sai6_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(155), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(65), 8, GFLAGS), > + GATE(HCLK_SAI6_8CH, "hclk_sai6_8ch", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 9, GFLAGS), > + GATE(HCLK_SPDIF_TX2, "hclk_spdif_tx2", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 10, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX2, "mclk_spdif_tx2", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(156), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(65), 13, GFLAGS), > + GATE(HCLK_SPDIF_RX2, "hclk_spdif_rx2", "hclk_vo0_root", 0, > + RK3576_CLKGATE_CON(65), 14, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX2, "mclk_spdif_rx2", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(156), 13, 2, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(65), 15, GFLAGS), > + > + /* vo1 */ > + COMPOSITE(ACLK_VO1_ROOT, "aclk_vo1_root", gpll_cpll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(158), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(67), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", > mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(158), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(67), 2, GFLAGS), > + COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_100m_50m_24m_p, > 0, > + RK3576_CLKSEL_CON(158), 9, 2, MFLAGS, > + RK3576_CLKGATE_CON(67), 3, GFLAGS), > + COMPOSITE(MCLK_SAI8_8CH_SRC, "mclk_sai8_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(157), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(66), 1, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI8_8CH, "mclk_sai8_8ch", mclk_sai8_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(157), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(66), 2, GFLAGS), > + GATE(HCLK_SAI8_8CH, "hclk_sai8_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(66), 0, GFLAGS), > + COMPOSITE(MCLK_SAI7_8CH_SRC, "mclk_sai7_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(159), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 8, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI7_8CH, "mclk_sai7_8ch", mclk_sai7_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(159), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(67), 9, GFLAGS), > + GATE(HCLK_SAI7_8CH, "hclk_sai7_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 10, GFLAGS), > + GATE(HCLK_SPDIF_TX3, "hclk_spdif_tx3", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 11, GFLAGS), > + GATE(HCLK_SPDIF_TX4, "hclk_spdif_tx4", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 12, GFLAGS), > + GATE(HCLK_SPDIF_TX5, "hclk_spdif_tx5", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(67), 13, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX3, "mclk_spdif_tx3", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(160), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 14, GFLAGS), > + COMPOSITE_NOMUX(CLK_AUX16MHZ_0, "clk_aux16mhz_0", "gpll", 0, > + RK3576_CLKSEL_CON(161), 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(67), 15, GFLAGS), > + GATE(ACLK_DP0, "aclk_dp0", "aclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 0, GFLAGS), > + GATE(PCLK_DP0, "pclk_dp0", "pclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 1, GFLAGS), > + GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 4, GFLAGS), > + GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 5, GFLAGS), > + GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 6, GFLAGS), > + GATE(CLK_TRNG1_SKP, "clk_trng1_skp", "aclk_hdcp1", 0, > + RK3576_CLKGATE_CON(68), 7, GFLAGS), > + GATE(HCLK_SAI9_8CH, "hclk_sai9_8ch", "hclk_vo1_root", 0, > + RK3576_CLKGATE_CON(68), 9, GFLAGS), > + COMPOSITE(MCLK_SAI9_8CH_SRC, "mclk_sai9_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(162), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 10, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI9_8CH, "mclk_sai9_8ch", mclk_sai9_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(162), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(68), 11, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX4, "mclk_spdif_tx4", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(163), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 12, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX5, "mclk_spdif_tx5", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(164), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(68), 13, GFLAGS), > + > + /* vpu */ > + COMPOSITE(ACLK_VPU_ROOT, "aclk_vpu_root", > gpll_spll_cpll_bpll_lpll_p, CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(118), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 0, GFLAGS), > + COMPOSITE_NODIV(ACLK_VPU_MID_ROOT, "aclk_vpu_mid_root", > mux_600m_400m_300m_24m_p, 0, > + RK3576_CLKSEL_CON(118), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 1, GFLAGS), > + COMPOSITE_NODIV(HCLK_VPU_ROOT, "hclk_vpu_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(118), 10, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 2, GFLAGS), > + COMPOSITE(ACLK_JPEG_ROOT, "aclk_jpeg_root", gpll_cpll_aupll_spll_p, > 0, > + RK3576_CLKSEL_CON(119), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 3, GFLAGS), > + COMPOSITE_NODIV(ACLK_VPU_LOW_ROOT, "aclk_vpu_low_root", > mux_400m_200m_100m_24m_p, 0, > + RK3576_CLKSEL_CON(119), 7, 2, MFLAGS, > + RK3576_CLKGATE_CON(49), 4, GFLAGS), > + GATE(HCLK_RGA2E_0, "hclk_rga2e_0", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(49), 13, GFLAGS), > + GATE(ACLK_RGA2E_0, "aclk_rga2e_0", "aclk_vpu_root", 0, > + RK3576_CLKGATE_CON(49), 14, GFLAGS), > + COMPOSITE(CLK_CORE_RGA2E_0, "clk_core_rga2e_0", > gpll_spll_cpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(120), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(49), 15, GFLAGS), > + GATE(ACLK_JPEG, "aclk_jpeg", "aclk_jpeg_root", 0, > + RK3576_CLKGATE_CON(50), 0, GFLAGS), > + GATE(HCLK_JPEG, "hclk_jpeg", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 1, GFLAGS), > + GATE(HCLK_VDPP, "hclk_vdpp", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 2, GFLAGS), > + GATE(ACLK_VDPP, "aclk_vdpp", "aclk_vpu_mid_root", 0, > + RK3576_CLKGATE_CON(50), 3, GFLAGS), > + COMPOSITE(CLK_CORE_VDPP, "clk_core_vdpp", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(120), 13, 1, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(50), 4, GFLAGS), > + GATE(HCLK_RGA2E_1, "hclk_rga2e_1", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 5, GFLAGS), > + GATE(ACLK_RGA2E_1, "aclk_rga2e_1", "aclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 6, GFLAGS), > + COMPOSITE(CLK_CORE_RGA2E_1, "clk_core_rga2e_1", > gpll_spll_cpll_bpll_lpll_p, 0, > + RK3576_CLKSEL_CON(121), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(50), 7, GFLAGS), > + MUX(0, "dclk_ebc_frac_src_p", gpll_cpll_vpll_aupll_24m_p, 0, > + RK3576_CLKSEL_CON(123), 0, 3, MFLAGS), > + COMPOSITE_FRAC(DCLK_EBC_FRAC_SRC, "dclk_ebc_frac_src", > "dclk_ebc_frac_src_p", 0, > + RK3576_CLKSEL_CON(122), 0, > + RK3576_CLKGATE_CON(50), 9, GFLAGS), > + GATE(ACLK_EBC, "aclk_ebc", "aclk_vpu_low_root", 0, > + RK3576_CLKGATE_CON(50), 11, GFLAGS), > + GATE(HCLK_EBC, "hclk_ebc", "hclk_vpu_root", 0, > + RK3576_CLKGATE_CON(50), 10, GFLAGS), > + COMPOSITE(DCLK_EBC, "dclk_ebc", dclk_ebc_p, CLK_SET_RATE_NO_REPARENT, > + RK3576_CLKSEL_CON(123), 12, 3, MFLAGS, 3, 9, DFLAGS, > + RK3576_CLKGATE_CON(50), 12, GFLAGS), > + > + /* vepu */ > + COMPOSITE_NODIV(HCLK_VEPU1_ROOT, "hclk_vepu1_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(178), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(78), 0, GFLAGS), > + COMPOSITE(ACLK_VEPU1_ROOT, "aclk_vepu1_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(180), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(79), 0, GFLAGS), > + GATE(HCLK_VEPU1, "hclk_vepu1", "hclk_vepu1_root", 0, > + RK3576_CLKGATE_CON(79), 3, GFLAGS), > + GATE(ACLK_VEPU1, "aclk_vepu1", "aclk_vepu1_root", 0, > + RK3576_CLKGATE_CON(79), 4, GFLAGS), > + COMPOSITE(CLK_VEPU1_CORE, "clk_vepu1_core", > gpll_cpll_spll_lpll_bpll_p, 0, > + RK3576_CLKSEL_CON(180), 11, 3, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(79), 5, GFLAGS), > + > + /* php */ > + COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_100m_50m_24m_p, > 0, > + RK3576_CLKSEL_CON(92), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(34), 0, GFLAGS), > + COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(92), 9, 1, MFLAGS, 4, 5, DFLAGS, > + RK3576_CLKGATE_CON(34), 7, GFLAGS), > + GATE(PCLK_PCIE0, "pclk_pcie0", "pclk_php_root", 0, > + RK3576_CLKGATE_CON(34), 13, GFLAGS), > + GATE(CLK_PCIE0_AUX, "clk_pcie0_aux", "xin24m", 0, > + RK3576_CLKGATE_CON(34), 14, GFLAGS), > + GATE(ACLK_PCIE0_MST, "aclk_pcie0_mst", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(34), 15, GFLAGS), > + GATE(ACLK_PCIE0_SLV, "aclk_pcie0_slv", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 0, GFLAGS), > + GATE(ACLK_PCIE0_DBI, "aclk_pcie0_dbi", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 1, GFLAGS), > + GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 3, GFLAGS), > + GATE(CLK_REF_USB3OTG1, "clk_ref_usb3otg1", "xin24m", 0, > + RK3576_CLKGATE_CON(35), 4, GFLAGS), > + GATE(CLK_SUSPEND_USB3OTG1, "clk_suspend_usb3otg1", "xin24m", 0, > + RK3576_CLKGATE_CON(35), 5, GFLAGS), > + GATE(ACLK_MMU0, "aclk_mmu0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 11, GFLAGS), > + GATE(ACLK_SLV_MMU0, "aclk_slv_mmu0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 13, GFLAGS), > + GATE(ACLK_MMU1, "aclk_mmu1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(35), 14, GFLAGS), > + GATE(ACLK_SLV_MMU1, "aclk_slv_mmu1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 0, GFLAGS), > + GATE(PCLK_PCIE1, "pclk_pcie1", "pclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 7, GFLAGS), > + GATE(CLK_PCIE1_AUX, "clk_pcie1_aux", "xin24m", 0, > + RK3576_CLKGATE_CON(36), 8, GFLAGS), > + GATE(ACLK_PCIE1_MST, "aclk_pcie1_mst", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 9, GFLAGS), > + GATE(ACLK_PCIE1_SLV, "aclk_pcie1_slv", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 10, GFLAGS), > + GATE(ACLK_PCIE1_DBI, "aclk_pcie1_dbi", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(36), 11, GFLAGS), > + COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(93), 7, 1, MFLAGS, 0, 7, DFLAGS, > + RK3576_CLKGATE_CON(37), 0, GFLAGS), > + COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(93), 15, 1, MFLAGS, 8, 7, DFLAGS, > + RK3576_CLKGATE_CON(37), 1, GFLAGS), > + GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(37), 2, GFLAGS), > + GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", CLK_IS_CRITICAL, > + RK3576_CLKGATE_CON(37), 3, GFLAGS), > + GATE(ACLK_SATA0, "aclk_sata0", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(37), 4, GFLAGS), > + GATE(ACLK_SATA1, "aclk_sata1", "aclk_php_root", 0, > + RK3576_CLKGATE_CON(37), 5, GFLAGS), > + > + /* audio */ > + COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(42), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(7), 1, GFLAGS), > + GATE(HCLK_ASRC_2CH_0, "hclk_asrc_2ch_0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 3, GFLAGS), > + GATE(HCLK_ASRC_2CH_1, "hclk_asrc_2ch_1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 4, GFLAGS), > + GATE(HCLK_ASRC_4CH_0, "hclk_asrc_4ch_0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 5, GFLAGS), > + GATE(HCLK_ASRC_4CH_1, "hclk_asrc_4ch_1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 6, GFLAGS), > + COMPOSITE(CLK_ASRC_2CH_0, "clk_asrc_2ch_0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(42), 7, 2, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 7, GFLAGS), > + COMPOSITE(CLK_ASRC_2CH_1, "clk_asrc_2ch_1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(42), 14, 2, MFLAGS, 9, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 8, GFLAGS), > + COMPOSITE(CLK_ASRC_4CH_0, "clk_asrc_4ch_0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(43), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 9, GFLAGS), > + COMPOSITE(CLK_ASRC_4CH_1, "clk_asrc_4ch_1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(43), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 10, GFLAGS), > + COMPOSITE(MCLK_SAI0_8CH_SRC, "mclk_sai0_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(44), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(7), 11, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI0_8CH, "mclk_sai0_8ch", mclk_sai0_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(44), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(7), 12, GFLAGS), > + GATE(HCLK_SAI0_8CH, "hclk_sai0_8ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 13, GFLAGS), > + GATE(HCLK_SPDIF_RX0, "hclk_spdif_rx0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(7), 14, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX0, "mclk_spdif_rx0", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(45), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(7), 15, GFLAGS), > + GATE(HCLK_SPDIF_RX1, "hclk_spdif_rx1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 0, GFLAGS), > + COMPOSITE(MCLK_SPDIF_RX1, "mclk_spdif_rx1", gpll_cpll_aupll_p, 0, > + RK3576_CLKSEL_CON(45), 12, 2, MFLAGS, 7, 5, DFLAGS, > + RK3576_CLKGATE_CON(8), 1, GFLAGS), > + COMPOSITE(MCLK_SAI1_8CH_SRC, "mclk_sai1_8ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(46), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 4, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI1_8CH, "mclk_sai1_8ch", mclk_sai1_8ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(46), 11, 1, MFLAGS, > + RK3576_CLKGATE_CON(8), 5, GFLAGS), > + GATE(HCLK_SAI1_8CH, "hclk_sai1_8ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 6, GFLAGS), > + COMPOSITE(MCLK_SAI2_2CH_SRC, "mclk_sai2_2ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(47), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 7, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI2_2CH, "mclk_sai2_2ch", mclk_sai2_2ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(47), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(8), 8, GFLAGS), > + GATE(HCLK_SAI2_2CH, "hclk_sai2_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 10, GFLAGS), > + COMPOSITE(MCLK_SAI3_2CH_SRC, "mclk_sai3_2ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(48), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 11, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI3_2CH, "mclk_sai3_2ch", mclk_sai3_2ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(48), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(8), 12, GFLAGS), > + GATE(HCLK_SAI3_2CH, "hclk_sai3_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(8), 14, GFLAGS), > + COMPOSITE(MCLK_SAI4_2CH_SRC, "mclk_sai4_2ch_src", audio_frac_int_p, > 0, > + RK3576_CLKSEL_CON(49), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(8), 15, GFLAGS), > + COMPOSITE_NODIV(MCLK_SAI4_2CH, "mclk_sai4_2ch", mclk_sai4_2ch_p, > CLK_SET_RATE_PARENT, > + RK3576_CLKSEL_CON(49), 11, 2, MFLAGS, > + RK3576_CLKGATE_CON(9), 0, GFLAGS), > + GATE(HCLK_SAI4_2CH, "hclk_sai4_2ch", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 2, GFLAGS), > + GATE(HCLK_ACDCDIG_DSM, "hclk_acdcdig_dsm", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 3, GFLAGS), > + GATE(MCLK_ACDCDIG_DSM, "mclk_acdcdig_dsm", "mclk_sai4_2ch", 0, > + RK3576_CLKGATE_CON(9), 4, GFLAGS), > + COMPOSITE(CLK_PDM1, "clk_pdm1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(50), 9, 3, MFLAGS, 0, 9, DFLAGS, > + RK3576_CLKGATE_CON(9), 5, GFLAGS), > + GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 7, GFLAGS), > + GATE(CLK_PDM1_OUT, "clk_pdm1_out", "clk_pdm1", 0, > + RK3576_CLKGATE_CON(3), 5, GFLAGS), > + COMPOSITE(MCLK_PDM1, "mclk_pdm1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(51), 5, 3, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(9), 8, GFLAGS), > + GATE(HCLK_SPDIF_TX0, "hclk_spdif_tx0", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 9, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX0, "mclk_spdif_tx0", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(52), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(9), 10, GFLAGS), > + GATE(HCLK_SPDIF_TX1, "hclk_spdif_tx1", "hclk_audio_root", 0, > + RK3576_CLKGATE_CON(9), 11, GFLAGS), > + COMPOSITE(MCLK_SPDIF_TX1, "mclk_spdif_tx1", audio_frac_int_p, 0, > + RK3576_CLKSEL_CON(53), 8, 3, MFLAGS, 0, 8, DFLAGS, > + RK3576_CLKGATE_CON(9), 12, GFLAGS), > + GATE(CLK_SAI1_MCLKOUT, "clk_sai1_mclkout", "mclk_sai1_8ch", 0, > + RK3576_CLKGATE_CON(9), 13, GFLAGS), > + GATE(CLK_SAI2_MCLKOUT, "clk_sai2_mclkout", "mclk_sai2_2ch", 0, > + RK3576_CLKGATE_CON(9), 14, GFLAGS), > + GATE(CLK_SAI3_MCLKOUT, "clk_sai3_mclkout", "mclk_sai3_2ch", 0, > + RK3576_CLKGATE_CON(9), 15, GFLAGS), > + GATE(CLK_SAI4_MCLKOUT, "clk_sai4_mclkout", "mclk_sai4_2ch", 0, > + RK3576_CLKGATE_CON(10), 0, GFLAGS), > + GATE(CLK_SAI0_MCLKOUT, "clk_sai0_mclkout", "mclk_sai0_8ch", 0, > + RK3576_CLKGATE_CON(10), 1, GFLAGS), > + > + /* sdgmac */ > + COMPOSITE_NODIV(HCLK_SDGMAC_ROOT, "hclk_sdgmac_root", > mux_200m_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(103), 0, 2, MFLAGS, > + RK3576_CLKGATE_CON(42), 0, GFLAGS), > + COMPOSITE(ACLK_SDGMAC_ROOT, "aclk_sdgmac_root", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(103), 7, 1, MFLAGS, 2, 5, DFLAGS, > + RK3576_CLKGATE_CON(42), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_SDGMAC_ROOT, "pclk_sdgmac_root", > mux_100m_50m_24m_p, 0, > + RK3576_CLKSEL_CON(103), 8, 2, MFLAGS, > + RK3576_CLKGATE_CON(42), 2, GFLAGS), > + GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 7, GFLAGS), > + GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 8, GFLAGS), > + GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 9, GFLAGS), > + GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 10, GFLAGS), > + COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(104), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(42), 11, GFLAGS), > + GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(42), 12, GFLAGS), > + COMPOSITE(CLK_GMAC1_PTP_REF_SRC, "clk_gmac1_ptp_ref_src", > clk_gmac1_ptp_ref_src_p, 0, > + RK3576_CLKSEL_CON(104), 13, 2, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(42), 15, GFLAGS), > + COMPOSITE(CLK_GMAC0_PTP_REF_SRC, "clk_gmac0_ptp_ref_src", > clk_gmac0_ptp_ref_src_p, 0, > + RK3576_CLKSEL_CON(105), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 0, GFLAGS), > + GATE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", "clk_gmac1_ptp_ref_src", > 0, > + RK3576_CLKGATE_CON(42), 13, GFLAGS), > + GATE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", "clk_gmac0_ptp_ref_src", > 0, > + RK3576_CLKGATE_CON(42), 14, GFLAGS), > + COMPOSITE(CCLK_SRC_SDMMC0, "cclk_src_sdmmc0", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(105), 13, 2, MFLAGS, 7, 6, DFLAGS, > + RK3576_CLKGATE_CON(43), 1, GFLAGS), > + GATE(HCLK_SDMMC0, "hclk_sdmmc0", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 2, GFLAGS), > + COMPOSITE(SCLK_FSPI1_X2, "sclk_fspi1_x2", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(106), 6, 2, MFLAGS, 0, 6, DFLAGS, > + RK3576_CLKGATE_CON(43), 3, GFLAGS), > + GATE(HCLK_FSPI1, "hclk_fspi1", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 4, GFLAGS), > + COMPOSITE(ACLK_DSMC_ROOT, "aclk_dsmc_root", gpll_cpll_p, > CLK_IS_CRITICAL, > + RK3576_CLKSEL_CON(106), 13, 1, MFLAGS, 8, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 5, GFLAGS), > + GATE(ACLK_DSMC, "aclk_dsmc", "aclk_dsmc_root", 0, > + RK3576_CLKGATE_CON(43), 7, GFLAGS), > + GATE(PCLK_DSMC, "pclk_dsmc", "pclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 8, GFLAGS), > + COMPOSITE(CLK_DSMC_SYS, "clk_dsmc_sys", gpll_cpll_p, 0, > + RK3576_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 9, GFLAGS), > + GATE(HCLK_HSGPIO, "hclk_hsgpio", "hclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 10, GFLAGS), > + COMPOSITE(CLK_HSGPIO_TX, "clk_hsgpio_tx", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 11, GFLAGS), > + COMPOSITE(CLK_HSGPIO_RX, "clk_hsgpio_rx", gpll_cpll_24m_p, 0, > + RK3576_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS, > + RK3576_CLKGATE_CON(43), 12, GFLAGS), > + GATE(ACLK_HSGPIO, "aclk_hsgpio", "aclk_sdgmac_root", 0, > + RK3576_CLKGATE_CON(43), 13, GFLAGS), > + > + /* phpphy */ > + GATE(PCLK_PHPPHY_ROOT, "pclk_phpphy_root", "pclk_bus_root", > CLK_IS_CRITICAL, > + RK3576_PHP_CLKGATE_CON(0), 2, GFLAGS), > + GATE(PCLK_PCIE2_COMBOPHY0, "pclk_pcie2_combophy0", > "pclk_phpphy_root", 0, > + RK3576_PHP_CLKGATE_CON(0), 5, GFLAGS), > + GATE(PCLK_PCIE2_COMBOPHY1, "pclk_pcie2_combophy1", > "pclk_phpphy_root", 0, > + RK3576_PHP_CLKGATE_CON(0), 7, GFLAGS), > + COMPOSITE_NOMUX(CLK_PCIE_100M_SRC, "clk_pcie_100m_src", "ppll", 0, > + RK3576_PHP_CLKSEL_CON(0), 2, 5, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 1, GFLAGS), > + COMPOSITE_NOMUX(CLK_PCIE_100M_NDUTY_SRC, "clk_pcie_100m_nduty_src", > "ppll", 0, > + RK3576_PHP_CLKSEL_CON(0), 7, 5, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 2, GFLAGS), > + COMPOSITE_NODIV(CLK_REF_PCIE0_PHY, "clk_ref_pcie0_phy", > clk_ref_pcie0_phy_p, 0, > + RK3576_PHP_CLKSEL_CON(0), 12, 2, MFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 5, GFLAGS), > + COMPOSITE_NODIV(CLK_REF_PCIE1_PHY, "clk_ref_pcie1_phy", > clk_ref_pcie0_phy_p, 0, > + RK3576_PHP_CLKSEL_CON(0), 14, 2, MFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 8, GFLAGS), > + COMPOSITE_NOMUX(CLK_REF_MPHY_26M, "clk_ref_mphy_26m", "ppll", > CLK_IS_CRITICAL, > + RK3576_PHP_CLKSEL_CON(1), 0, 8, DFLAGS, > + RK3576_PHP_CLKGATE_CON(1), 9, GFLAGS), > + > + /* pmu */ > + GATE(CLK_200M_PMU_SRC, "clk_200m_pmu_src", "clk_gpll_div6", 0, > + RK3576_PMU_CLKGATE_CON(3), 2, GFLAGS), > + COMPOSITE_NOMUX(CLK_100M_PMU_SRC, "clk_100m_pmu_src", "cpll", 0, > + RK3576_PMU_CLKSEL_CON(4), 4, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 3, GFLAGS), > + FACTOR_GATE(CLK_50M_PMU_SRC, "clk_50m_pmu_src", "clk_100m_pmu_src", > 0, 1, 2, > + RK3576_PMU_CLKGATE_CON(3), 4, GFLAGS), > + COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", > mux_pmu200m_pmu100m_pmu50m_24m_p, CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(4), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", > mux_pmu200m_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 2, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_PMU0_ROOT, "pclk_pmu0_root", > mux_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(20), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(7), 0, GFLAGS), > + GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 3, GFLAGS), > + GATE(PCLK_PMU1_ROOT, "pclk_pmu1_root", "pclk_pmu0_root", > CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 9, GFLAGS), > + GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu1_root", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(3), 15, GFLAGS), > + GATE(CLK_PMU1, "clk_pmu1", "xin24m", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(4), 2, GFLAGS), > + GATE(PCLK_PMUPHY_ROOT, "pclk_pmuphy_root", "pclk_pmu1_root", > CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(5), 0, GFLAGS), > + GATE(PCLK_HDPTX_APB, "pclk_hdptx_apb", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 1, GFLAGS), > + GATE(PCLK_MIPI_DCPHY, "pclk_mipi_dcphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 2, GFLAGS), > + GATE(PCLK_CSIDPHY, "pclk_csidphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 8, GFLAGS), > + GATE(PCLK_USBDPPHY, "pclk_usbdpphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(0), 12, GFLAGS), > + COMPOSITE_NOMUX(CLK_PMUPHY_REF_SRC, "clk_pmuphy_ref_src", "cpll", 0, > + RK3576_PMU_CLKSEL_CON(0), 0, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(0), 13, GFLAGS), > + GATE(CLK_USBDP_COMBO_PHY_IMMORTAL, "clk_usbdp_combo_phy_immortal", > "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(0), 15, GFLAGS), > + GATE(CLK_HDMITXHPD, "clk_hdmitxhpd", "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(1), 13, GFLAGS), > + GATE(PCLK_MPHY, "pclk_mphy", "pclk_pmuphy_root", 0, > + RK3576_PMU_CLKGATE_CON(2), 0, GFLAGS), > + MUX(CLK_REF_OSC_MPHY, "clk_ref_osc_mphy", clk_ref_osc_mphy_p, 0, > + RK3576_PMU_CLKSEL_CON(3), 0, 2, MFLAGS), > + GATE(CLK_REF_UFS_CLKOUT, "clk_ref_ufs_clkout", "clk_ref_osc_mphy", 0, > + RK3576_PMU_CLKGATE_CON(2), 5, GFLAGS), > + GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", 0, > + RK3576_PMU_CLKGATE_CON(3), 12, GFLAGS), > + COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 14, 1, MFLAGS, 9, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(3), 14, GFLAGS), > + GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 5, GFLAGS), > + COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(4), 15, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 6, GFLAGS), > + GATE(PCLK_PMUTIMER, "pclk_pmutimer", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 7, GFLAGS), > + COMPOSITE_NODIV(CLK_PMUTIMER_ROOT, "clk_pmutimer_root", > mux_pmu100m_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(5), 0, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 8, GFLAGS), > + GATE(CLK_PMUTIMER0, "clk_pmutimer0", "clk_pmutimer_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 9, GFLAGS), > + GATE(CLK_PMUTIMER1, "clk_pmutimer1", "clk_pmutimer_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 10, GFLAGS), > + GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(4), 11, GFLAGS), > + COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", mux_pmu100m_pmu50m_24m_p, > 0, > + RK3576_PMU_CLKSEL_CON(5), 2, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(4), 12, GFLAGS), > + GATE(CLK_PMU1PWM_OSC, "clk_pmu1pwm_osc", "xin24m", 0, > + RK3576_PMU_CLKGATE_CON(4), 13, GFLAGS), > + GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 1, GFLAGS), > + COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", > mux_pmu200m_pmu100m_pmu50m_24m_p, 0, > + RK3576_PMU_CLKSEL_CON(6), 7, 2, MFLAGS, > + RK3576_PMU_CLKGATE_CON(5), 2, GFLAGS), > + COMPOSITE_NODIV(SCLK_UART1, "sclk_uart1", uart1_p, 0, > + RK3576_PMU_CLKSEL_CON(8), 0, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(5), 5, GFLAGS), > + GATE(PCLK_UART1, "pclk_uart1", "pclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 6, GFLAGS), > + GATE(CLK_PDM0, "clk_pdm0", "clk_pdm0_src_top", 0, > + RK3576_PMU_CLKGATE_CON(5), 13, GFLAGS), > + GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(5), 15, GFLAGS), > + GATE(MCLK_PDM0, "mclk_pdm0", "mclk_pdm0_src_top", 0, > + RK3576_PMU_CLKGATE_CON(6), 0, GFLAGS), > + GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0, > + RK3576_PMU_CLKGATE_CON(6), 1, GFLAGS), > + GATE(CLK_PDM0_OUT, "clk_pdm0_out", "clk_pdm0", 0, > + RK3576_PMU_CLKGATE_CON(6), 8, GFLAGS), > + COMPOSITE(CLK_HPTIMER_SRC, "clk_hptimer_src", cpll_24m_p, > CLK_IS_CRITICAL, > + RK3576_PMU_CLKSEL_CON(11), 6, 1, MFLAGS, 1, 5, DFLAGS, > + RK3576_PMU_CLKGATE_CON(6), 10, GFLAGS), > + GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0, > + RK3576_PMU_CLKGATE_CON(7), 6, GFLAGS), > + COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0, > + RK3576_PMU_CLKSEL_CON(20), 2, 1, MFLAGS, > + RK3576_PMU_CLKGATE_CON(7), 7, GFLAGS), > + GATE(CLK_OSC0_PMU1, "clk_osc0_pmu1", "xin24m", CLK_IS_CRITICAL, > + RK3576_PMU_CLKGATE_CON(7), 8, GFLAGS), > + GATE(CLK_PMU1PWM_RC, "clk_pmu1pwm_rc", "clk_pvtm_clkout", 0, > + RK3576_PMU_CLKGATE_CON(5), 7, GFLAGS), > + > + /* phy ref */ > + MUXGRF(CLK_PHY_REF_SRC, "clk_phy_ref_src", clk_phy_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 4, 1, MFLAGS), > + MUXGRF(CLK_USBPHY_REF_SRC, "clk_usbphy_ref_src", > clk_usbphy_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 2, 1, MFLAGS), > + MUXGRF(CLK_CPLL_REF_SRC, "clk_cpll_ref_src", clk_cpll_ref_src_p, 0, > + RK3576_PMU0_GRF_OSC_CON6, 1, 1, MFLAGS), > + MUXGRF(CLK_AUPLL_REF_SRC, "clk_aupll_ref_src", clk_aupll_ref_src_p, > 0, > + RK3576_PMU0_GRF_OSC_CON6, 0, 1, MFLAGS), > + > + /* secure ns */ > + COMPOSITE_NODIV(ACLK_SECURE_NS, "aclk_secure_ns", > mux_350m_175m_116m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 0, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 0, GFLAGS), > + COMPOSITE_NODIV(HCLK_SECURE_NS, "hclk_secure_ns", > mux_175m_116m_58m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 2, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 1, GFLAGS), > + COMPOSITE_NODIV(PCLK_SECURE_NS, "pclk_secure_ns", > mux_116m_58m_24m_p, CLK_IS_CRITICAL, > + RK3576_SECURE_NS_CLKSEL_CON(0), 4, 2, MFLAGS, > + RK3576_SECURE_NS_CLKGATE_CON(0), 2, GFLAGS), > + GATE(HCLK_CRYPTO_NS, "hclk_crypto_ns", "hclk_secure_ns", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 3, GFLAGS), > + GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_secure_ns", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 8, GFLAGS), > + GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0, > + RK3576_SECURE_NS_CLKGATE_CON(0), 9, GFLAGS), > + GATE(ACLK_CRYPTO_NS, "aclk_crypto_ns", "aclk_secure_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 14, GFLAGS), > + GATE(HCLK_TRNG_NS, "hclk_trng_ns", "hclk_secure_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 13, GFLAGS), > + GATE(CLK_PKA_CRYPTO_NS, "clk_pka_crypto_ns", "clk_pka_crypto_s", 0, > + RK3576_NON_SECURE_GATING_CON00, 1, GFLAGS), > + > + /* io */ > + GATE(CLK_VICAP_I0CLK, "clk_vicap_i0clk", "clk_csihost0_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 1, GFLAGS), > + GATE(CLK_VICAP_I1CLK, "clk_vicap_i1clk", "clk_csihost1_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 2, GFLAGS), > + GATE(CLK_VICAP_I2CLK, "clk_vicap_i2clk", "clk_csihost2_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 3, GFLAGS), > + GATE(CLK_VICAP_I3CLK, "clk_vicap_i3clk", "clk_csihost3_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 4, GFLAGS), > + GATE(CLK_VICAP_I4CLK, "clk_vicap_i4clk", "clk_csihost4_clkdata_i", 0, > + RK3576_CLKGATE_CON(59), 5, GFLAGS), > +}; > + > +static void __init rk3576_clk_init(struct device_node *np) > +{ > + struct rockchip_clk_provider *ctx; > + unsigned long clk_nr_clks; > + void __iomem *reg_base; > + struct regmap *grf; > + > + clk_nr_clks = rockchip_clk_find_max_clk_id(rk3576_clk_branches, > + ARRAY_SIZE(rk3576_clk_branches)) + 1; > + > + grf = syscon_regmap_lookup_by_compatible("rockchip,rk3576-pmu0-grf"); > + if (IS_ERR(grf)) { > + pr_err("%s: could not get PMU0 GRF syscon\n", __func__); > + return; > + } > + > + reg_base = of_iomap(np, 0); > + if (!reg_base) { > + pr_err("%s: could not map cru region\n", __func__); > + return; > + } > + > + ctx = rockchip_clk_init(np, reg_base, clk_nr_clks); > + if (IS_ERR(ctx)) { > + pr_err("%s: rockchip clk init failed\n", __func__); > + iounmap(reg_base); > + return; > + } > + > + ctx->grf = grf; > + > + rockchip_clk_register_plls(ctx, rk3576_pll_clks, > + ARRAY_SIZE(rk3576_pll_clks), > + RK3576_GRF_SOC_STATUS0); > + > + rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l", > + mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p), > + &rk3576_cpulclk_data, rk3576_cpulclk_rates, > + ARRAY_SIZE(rk3576_cpulclk_rates)); > + rockchip_clk_register_armclk(ctx, ARMCLK_B, "armclk_b", > + mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p), > + &rk3576_cpubclk_data, rk3576_cpubclk_rates, > + ARRAY_SIZE(rk3576_cpubclk_rates)); > + > + rockchip_clk_register_branches(ctx, rk3576_clk_branches, > + ARRAY_SIZE(rk3576_clk_branches)); > + > + rk3576_rst_init(np, reg_base); > + > + rockchip_register_restart_notifier(ctx, RK3576_GLB_SRST_FST, NULL); > + > + rockchip_clk_of_add_provider(np, ctx); > +} > + > +CLK_OF_DECLARE(rk3576_cru, "rockchip,rk3576-cru", rk3576_clk_init); > + > +#ifdef MODULE > +struct clk_rk3576_inits { > + void (*inits)(struct device_node *np); > +}; > + > +static const struct clk_rk3576_inits clk_rk3576_cru_init = { > + .inits = rk3576_clk_init, > +}; > + > +static const struct of_device_id clk_rk3576_match_table[] = { > + { > + .compatible = "rockchip,rk3576-cru", > + .data = &clk_rk3576_cru_init, > + }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, clk_rk3576_match_table); > + > +static int clk_rk3576_probe(struct platform_device *pdev) > +{ > + struct device_node *np = pdev->dev.of_node; > + const struct of_device_id *match; > + const struct clk_rk3576_inits *init_data; > + > + match = of_match_device(clk_rk3576_match_table, &pdev->dev); > + if (!match || !match->data) > + return -EINVAL; > + > + init_data = match->data; > + if (init_data->inits) > + init_data->inits(np); > + > + return 0; > +} > + > +static struct platform_driver clk_rk3576_driver = { > + .probe = clk_rk3576_probe, > + .driver = { > + .name = "clk-rk3576", > + .of_match_table = clk_rk3576_match_table, > + .suppress_bind_attrs = true, > + }, > +}; > +module_platform_driver(clk_rk3576_driver); > + > +MODULE_DESCRIPTION("Rockchip RK3576 Clock Driver"); > +MODULE_LICENSE("GPL"); > +#endif /* MODULE */ > diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h > index 40fc0e4703c1..f1957e1c1178 100644 > --- a/drivers/clk/rockchip/clk.h > +++ b/drivers/clk/rockchip/clk.h > @@ -235,6 +235,58 @@ struct clk; > #define RK3568_PMU_CLKGATE_CON(x) ((x) * 0x4 + 0x180) > #define RK3568_PMU_SOFTRST_CON(x) ((x) * 0x4 + 0x200) > > +#define RK3576_PHP_CRU_BASE 0x8000 > +#define RK3576_SECURE_NS_CRU_BASE 0x10000 > +#define RK3576_PMU_CRU_BASE 0x20000 > +#define RK3576_BIGCORE_CRU_BASE 0x38000 > +#define RK3576_LITCORE_CRU_BASE 0x40000 > +#define RK3576_CCI_CRU_BASE 0x48000 > + > +#define RK3576_PLL_CON(x) RK2928_PLL_CON(x) > +#define RK3576_MODE_CON0 0x280 > +#define RK3576_BPLL_MODE_CON0 (RK3576_BIGCORE_CRU_BASE + 0x280) > +#define RK3576_LPLL_MODE_CON0 (RK3576_LITCORE_CRU_BASE + 0x280) > +#define RK3576_PPLL_MODE_CON0 (RK3576_PHP_CRU_BASE + 0x280) > +#define RK3576_CLKSEL_CON(x) ((x) * 0x4 + 0x300) > +#define RK3576_CLKGATE_CON(x) ((x) * 0x4 + 0x800) > +#define RK3576_SOFTRST_CON(x) ((x) * 0x4 + 0xa00) > +#define RK3576_GLB_CNT_TH 0xc00 > +#define RK3576_GLB_SRST_FST 0xc08 > +#define RK3576_GLB_SRST_SND 0xc0c > +#define RK3576_GLB_RST_CON 0xc10 > +#define RK3576_GLB_RST_ST 0xc04 > +#define RK3576_SDIO_CON0 0xC24 > +#define RK3576_SDIO_CON1 0xC28 > +#define RK3576_SDMMC_CON0 0xC30 > +#define RK3576_SDMMC_CON1 0xC34 > + > +#define RK3576_PHP_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + > 0x300) > +#define RK3576_PHP_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + > 0x800) > +#define RK3576_PHP_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE + > 0xa00) > + > +#define RK3576_PMU_PLL_CON(x) ((x) * 0x4 + RK3576_PHP_CRU_BASE) > +#define RK3576_PMU_CLKSEL_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + > 0x300) > +#define RK3576_PMU_CLKGATE_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + > 0x800) > +#define RK3576_PMU_SOFTRST_CON(x) ((x) * 0x4 + RK3576_PMU_CRU_BASE + > 0xa00) > + > +#define RK3576_SECURE_NS_CLKSEL_CON(x) ((x) * 0x4 + > RK3576_SECURE_NS_CRU_BASE + 0x300) > +#define RK3576_SECURE_NS_CLKGATE_CON(x) ((x) * 0x4 + > RK3576_SECURE_NS_CRU_BASE + 0x800) > +#define RK3576_SECURE_NS_SOFTRST_CON(x) ((x) * 0x4 + > RK3576_SECURE_NS_CRU_BASE + 0xa00) > + > +#define RK3576_CCI_CLKSEL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + > 0x300) > +#define RK3576_CCI_CLKGATE_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + > 0x800) > +#define RK3576_CCI_SOFTRST_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE + > 0xa00) > + > +#define RK3576_BPLL_CON(x) ((x) * 0x4 + RK3576_BIGCORE_CRU_BASE) > +#define RK3576_BIGCORE_CLKSEL_CON(x) ((x) * 0x4 + > RK3576_BIGCORE_CRU_BASE + 0x300) > +#define RK3576_BIGCORE_CLKGATE_CON(x) ((x) * 0x4 + > RK3576_BIGCORE_CRU_BASE + 0x800) > +#define RK3576_BIGCORE_SOFTRST_CON(x) ((x) * 0x4 + > RK3576_BIGCORE_CRU_BASE + 0xa00) > +#define RK3576_LPLL_CON(x) ((x) * 0x4 + RK3576_CCI_CRU_BASE) > +#define RK3576_LITCORE_CLKSEL_CON(x) ((x) * 0x4 + > RK3576_LITCORE_CRU_BASE + 0x300) > +#define RK3576_LITCORE_CLKGATE_CON(x) ((x) * 0x4 + > RK3576_LITCORE_CRU_BASE + 0x800) > +#define RK3576_LITCORE_SOFTRST_CON(x) ((x) * 0x4 + > RK3576_LITCORE_CRU_BASE + 0xa00) > +#define RK3576_NON_SECURE_GATING_CON00 0xc48 > + > #define RK3588_PHP_CRU_BASE 0x8000 > #define RK3588_PMU_CRU_BASE 0x30000 > #define RK3588_BIGCORE0_CRU_BASE 0x50000 > @@ -1026,6 +1078,7 @@ static inline void > rockchip_register_softrst(struct device_node *np, > return rockchip_register_softrst_lut(np, NULL, num_regs, base, > flags); > } > > +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base); > void rk3588_rst_init(struct device_node *np, void __iomem *reg_base); > > #endif > diff --git a/drivers/clk/rockchip/rst-rk3576.c > b/drivers/clk/rockchip/rst-rk3576.c > new file mode 100644 > index 000000000000..3380d73c86c5 > --- /dev/null > +++ b/drivers/clk/rockchip/rst-rk3576.c > @@ -0,0 +1,652 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. > + * Copyright (c) 2024 Collabora Ltd. > + * Author: Detlev Casanova <detlev.casanova@collabora.com> > + * Based on Sebastien Reichel's implementation for RK3588 > + */ > + > +#include <linux/module.h> > +#include <linux/of.h> > +#include <dt-bindings/reset/rockchip,rk3576-cru.h> > +#include "clk.h" > + > +/* 0x27200000 + 0x0A00 */ > +#define RK3576_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + > bit) > +/* 0x27208000 + 0x0A00 */ > +#define RK3576_PHPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + > reg * 16 + bit) > +/* 0x27210000 + 0x0A00 */ > +#define RK3576_SECURENSCRU_RESET_OFFSET(id, reg, bit) [id] = > (0x10000*4 + reg * 16 + bit) > +/* 0x27220000 + 0x0A00 */ > +#define RK3576_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x20000*4 + > reg * 16 + bit) > + > +/* mapping table for reset ID to register offset */ > +static const int rk3576_register_offset[] = { > + /* SOFTRST_CON01 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_TOP_MID_BIU, 1, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_SECURE_HIGH_BIU, 1, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_TOP_BIU, 1, 14), > + > + /* SOFTRST_CON02 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO0VOP_CHANNEL_BIU, 2, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_VO0VOP_CHANNEL_BIU, 2, 1), > + > + /* SOFTRST_CON06 */ > + RK3576_CRU_RESET_OFFSET(SRST_BISRINTF, 6, 2), > + > + /* SOFTRST_CON07 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_0, 7, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_2CH_1, 7, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_0, 7, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_ASRC_4CH_1, 7, 6), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_0, 7, 7), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_2CH_1, 7, 8), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_0, 7, 9), > + RK3576_CRU_RESET_OFFSET(SRST_ASRC_4CH_1, 7, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI0_8CH, 7, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI0_8CH, 7, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX0, 7, 14), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX0, 7, 15), > + > + /* SOFTRST_CON08 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX1, 8, 0), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX1, 8, 1), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI1_8CH, 8, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI1_8CH, 8, 6), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI2_2CH, 8, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI2_2CH, 8, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI3_2CH, 8, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI3_2CH, 8, 14), > + > + /* SOFTRST_CON09 */ > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI4_2CH, 9, 0), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI4_2CH, 9, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_ACDCDIG_DSM, 9, 3), > + RK3576_CRU_RESET_OFFSET(SRST_M_ACDCDIG_DSM, 9, 4), > + RK3576_CRU_RESET_OFFSET(SRST_PDM1, 9, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 7), > + RK3576_CRU_RESET_OFFSET(SRST_M_PDM1, 9, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX0, 9, 9), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX0, 9, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX1, 9, 11), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX1, 9, 12), > + > + /* SOFTRST_CON11 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 11, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 11, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_CRU, 11, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_CAN0, 11, 6), > + RK3576_CRU_RESET_OFFSET(SRST_CAN0, 11, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_CAN1, 11, 8), > + RK3576_CRU_RESET_OFFSET(SRST_CAN1, 11, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2BUS, 11, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_VCCIO_IOC, 11, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_BIU, 11, 14), > + RK3576_CRU_RESET_OFFSET(SRST_KEY_SHIFT, 11, 15), > + > + /* SOFTRST_CON12 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C1, 12, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C2, 12, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C3, 12, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C4, 12, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C5, 12, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C6, 12, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C7, 12, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C8, 12, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_I2C9, 12, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT_BUSMCU, 12, 9), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_BUSMCU, 12, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_GIC, 12, 11), > + RK3576_CRU_RESET_OFFSET(SRST_I2C1, 12, 12), > + RK3576_CRU_RESET_OFFSET(SRST_I2C2, 12, 13), > + RK3576_CRU_RESET_OFFSET(SRST_I2C3, 12, 14), > + RK3576_CRU_RESET_OFFSET(SRST_I2C4, 12, 15), > + > + /* SOFTRST_CON13 */ > + RK3576_CRU_RESET_OFFSET(SRST_I2C5, 13, 0), > + RK3576_CRU_RESET_OFFSET(SRST_I2C6, 13, 1), > + RK3576_CRU_RESET_OFFSET(SRST_I2C7, 13, 2), > + RK3576_CRU_RESET_OFFSET(SRST_I2C8, 13, 3), > + RK3576_CRU_RESET_OFFSET(SRST_I2C9, 13, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_SARADC, 13, 6), > + RK3576_CRU_RESET_OFFSET(SRST_SARADC, 13, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_TSADC, 13, 8), > + RK3576_CRU_RESET_OFFSET(SRST_TSADC, 13, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART0, 13, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART2, 13, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART3, 13, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART4, 13, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART5, 13, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART6, 13, 15), > + > + /* SOFTRST_CON14 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_UART7, 14, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART8, 14, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART9, 14, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART10, 14, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_UART11, 14, 4), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART0, 14, 5), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART2, 14, 6), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART3, 14, 9), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART4, 14, 12), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART5, 14, 15), > + > + /* SOFTRST_CON15 */ > + RK3576_CRU_RESET_OFFSET(SRST_S_UART6, 15, 2), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART7, 15, 5), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART8, 15, 8), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART9, 15, 9), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART10, 15, 10), > + RK3576_CRU_RESET_OFFSET(SRST_S_UART11, 15, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI0, 15, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI1, 15, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI2, 15, 15), > + > + /* SOFTRST_CON16 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI3, 16, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_SPI4, 16, 1), > + RK3576_CRU_RESET_OFFSET(SRST_SPI0, 16, 2), > + RK3576_CRU_RESET_OFFSET(SRST_SPI1, 16, 3), > + RK3576_CRU_RESET_OFFSET(SRST_SPI2, 16, 4), > + RK3576_CRU_RESET_OFFSET(SRST_SPI3, 16, 5), > + RK3576_CRU_RESET_OFFSET(SRST_SPI4, 16, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT0, 16, 7), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT0, 16, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 16, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_PWM1, 16, 10), > + RK3576_CRU_RESET_OFFSET(SRST_PWM1, 16, 11), > + > + /* SOFTRST_CON17 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 17, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 17, 4), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER0, 17, 6), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER1, 17, 7), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER2, 17, 8), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER3, 17, 9), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER4, 17, 10), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER5, 17, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_BUSIOC, 17, 12), > + RK3576_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 17, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO1, 17, 15), > + > + /* SOFTRST_CON18 */ > + RK3576_CRU_RESET_OFFSET(SRST_GPIO1, 18, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO2, 18, 1), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO2, 18, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO3, 18, 3), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO3, 18, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPIO4, 18, 5), > + RK3576_CRU_RESET_OFFSET(SRST_GPIO4, 18, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DECOM, 18, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_DECOM, 18, 8), > + RK3576_CRU_RESET_OFFSET(SRST_D_DECOM, 18, 9), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER6, 18, 11), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER7, 18, 12), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER8, 18, 13), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER9, 18, 14), > + RK3576_CRU_RESET_OFFSET(SRST_TIMER10, 18, 15), > + > + /* SOFTRST_CON19 */ > + RK3576_CRU_RESET_OFFSET(SRST_TIMER11, 19, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC0, 19, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC1, 19, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMAC2, 19, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 19, 4), > + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_BUS, 19, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_I3C0, 19, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_I3C1, 19, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_BUS_CM0_BIU, 19, 11), > + RK3576_CRU_RESET_OFFSET(SRST_F_BUS_CM0_CORE, 19, 12), > + RK3576_CRU_RESET_OFFSET(SRST_T_BUS_CM0_JTAG, 19, 13), > + > + /* SOFTRST_CON20 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2PMU, 20, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_INTMUX2DDR, 20, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_BUS, 20, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_PWM2, 20, 4), > + RK3576_CRU_RESET_OFFSET(SRST_PWM2, 20, 5), > + RK3576_CRU_RESET_OFFSET(SRST_FREQ_PWM1, 20, 8), > + RK3576_CRU_RESET_OFFSET(SRST_COUNTER_PWM1, 20, 9), > + RK3576_CRU_RESET_OFFSET(SRST_I3C0, 20, 12), > + RK3576_CRU_RESET_OFFSET(SRST_I3C1, 20, 13), > + > + /* SOFTRST_CON21 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 21, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_BIU, 21, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 21, 3), > + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 21, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 21, 5), > + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH0, 21, 6), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 21, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH0, 21, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 21, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_HWLP_CH1, 21, 15), > + > + /* SOFTRST_CON22 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 22, 0), > + RK3576_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 22, 1), > + RK3576_CRU_RESET_OFFSET(SRST_DFI_CH1, 22, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 22, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 4), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 22, 6), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH0, 22, 9), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_SCRAMBLE_CH1, 22, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_AHB2APB, 22, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_AHB2APB, 22, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_DDR_BIU, 22, 14), > + RK3576_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 22, 15), > + > + /* SOFTRST_CON23 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 23, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 23, 2), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 23, 4), > + RK3576_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 23, 5), > + RK3576_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 23, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_WDT, 23, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_TIMER, 23, 8), > + RK3576_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 23, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_DDR_GRF, 23, 11), > + > + /* SOFTRST_CON25 */ > + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 25, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH0, 25, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH0, 25, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH0, 25, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH0, 25, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH0, 25, 6), > + > + /* SOFTRST_CON26 */ > + RK3576_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 26, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_0_CH1, 26, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_1_CH1, 26, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_2_CH1, 26, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_3_CH1, 26, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_4_CH1, 26, 6), > + > + /* SOFTRST_CON27 */ > + RK3576_CRU_RESET_OFFSET(SRST_REF_PVTPLL_DDR, 27, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_DDR, 27, 1), > + > + /* SOFTRST_CON28 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0, 28, 9), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 28, 11), > + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN0_BIU, 28, 12), > + > + /* SOFTRST_CON29 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1, 29, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 29, 2), > + RK3576_CRU_RESET_OFFSET(SRST_L_RKNN1_BIU, 29, 3), > + > + /* SOFTRST_CON31 */ > + RK3576_CRU_RESET_OFFSET(SRST_NPU_DAP, 31, 0), > + RK3576_CRU_RESET_OFFSET(SRST_L_NPUSUBSYS_BIU, 31, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 31, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 31, 10), > + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER0, 31, 12), > + RK3576_CRU_RESET_OFFSET(SRST_NPUTIMER1, 31, 13), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 31, 14), > + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 31, 15), > + > + /* SOFTRST_CON32 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNN_CBUF, 32, 0), > + RK3576_CRU_RESET_OFFSET(SRST_A_RVCORE0, 32, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 32, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_NPU, 32, 3), > + RK3576_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 32, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 32, 6), > + RK3576_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 32, 7), > + RK3576_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 32, 8), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKNNTOP_BIU, 32, 11), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKNN_CBUF, 32, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKNNTOP_BIU, 32, 13), > + > + /* SOFTRST_CON33 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 33, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 33, 3), > + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI, 33, 6), > + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI, 33, 7), > + RK3576_CRU_RESET_OFFSET(SRST_C_EMMC, 33, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_EMMC, 33, 9), > + RK3576_CRU_RESET_OFFSET(SRST_A_EMMC, 33, 10), > + RK3576_CRU_RESET_OFFSET(SRST_B_EMMC, 33, 11), > + RK3576_CRU_RESET_OFFSET(SRST_T_EMMC, 33, 12), > + > + /* SOFTRST_CON34 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_GRF, 34, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 34, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 34, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE0, 34, 13), > + RK3576_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 34, 15), > + > + /* SOFTRST_CON35 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 35, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU0, 35, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU0, 35, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU1, 35, 14), > + > + /* SOFTRST_CON36 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU1, 36, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_PCIE1, 36, 7), > + RK3576_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 36, 9), > + > + /* SOFTRST_CON37 */ > + RK3576_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 0), > + RK3576_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 1), > + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 2), > + RK3576_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 5), > + RK3576_CRU_RESET_OFFSET(SRST_ASIC1, 37, 6), > + RK3576_CRU_RESET_OFFSET(SRST_ASIC0, 37, 7), > + > + /* SOFTRST_CON40 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_CSIDPHY1, 40, 2), > + RK3576_CRU_RESET_OFFSET(SRST_SCAN_CSIDPHY1, 40, 3), > + > + /* SOFTRST_CON42 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_GRF, 42, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_SDGMAC_BIU, 42, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_SDGMAC_BIU, 42, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_SDGMAC_BIU, 42, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC0, 42, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_GMAC1, 42, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC0, 42, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_GMAC1, 42, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SDIO, 42, 12), > + > + /* SOFTRST_CON43 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SDMMC0, 43, 2), > + RK3576_CRU_RESET_OFFSET(SRST_S_FSPI1, 43, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_FSPI1, 43, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC_BIU, 43, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DSMC, 43, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_DSMC, 43, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_HSGPIO, 43, 10), > + RK3576_CRU_RESET_OFFSET(SRST_HSGPIO, 43, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_HSGPIO, 43, 13), > + > + /* SOFTRST_CON45 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC, 45, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_RKVDEC_BIU, 45, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_RKVDEC_BIU, 45, 6), > + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_HEVC_CA, 45, 8), > + RK3576_CRU_RESET_OFFSET(SRST_RKVDEC_CORE, 45, 9), > + > + /* SOFTRST_CON47 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_USB_BIU, 47, 3), > + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_BIU, 47, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 47, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_BIU, 47, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_MMU2, 47, 12), > + RK3576_CRU_RESET_OFFSET(SRST_A_SLV_MMU2, 47, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS_SYS, 47, 15), > + > + /* SOFTRST_CON48 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_UFS, 48, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_USBUFS_GRF, 48, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_UFS_GRF, 48, 2), > + > + /* SOFTRST_CON49 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VPU_BIU, 49, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG_BIU, 49, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA_BIU, 49, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP_BIU, 49, 11), > + RK3576_CRU_RESET_OFFSET(SRST_A_EBC_BIU, 49, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_0, 49, 13), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_0, 49, 14), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_0, 49, 15), > + > + /* SOFTRST_CON50 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_JPEG, 50, 0), > + RK3576_CRU_RESET_OFFSET(SRST_H_JPEG, 50, 1), > + RK3576_CRU_RESET_OFFSET(SRST_H_VDPP, 50, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_VDPP, 50, 3), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_VDPP, 50, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_RGA2E_1, 50, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_RGA2E_1, 50, 6), > + RK3576_CRU_RESET_OFFSET(SRST_CORE_RGA2E_1, 50, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_EBC, 50, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_EBC, 50, 11), > + RK3576_CRU_RESET_OFFSET(SRST_D_EBC, 50, 12), > + > + /* SOFTRST_CON51 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0_BIU, 51, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0_BIU, 51, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU0, 51, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU0, 51, 5), > + RK3576_CRU_RESET_OFFSET(SRST_VEPU0_CORE, 51, 6), > + > + /* SOFTRST_CON53 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_VI_BIU, 53, 3), > + RK3576_CRU_RESET_OFFSET(SRST_H_VI_BIU, 53, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_VI_BIU, 53, 5), > + RK3576_CRU_RESET_OFFSET(SRST_D_VICAP, 53, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_VICAP, 53, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_VICAP, 53, 8), > + RK3576_CRU_RESET_OFFSET(SRST_ISP0, 53, 10), > + RK3576_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 53, 11), > + > + /* SOFTRST_CON54 */ > + RK3576_CRU_RESET_OFFSET(SRST_CORE_VPSS, 54, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 54, 4), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 54, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 54, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 54, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 54, 8), > + > + /* SOFTRST_CON59 */ > + RK3576_CRU_RESET_OFFSET(SRST_CIFIN, 59, 0), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I0CLK, 59, 1), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I1CLK, 59, 2), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I2CLK, 59, 3), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I3CLK, 59, 4), > + RK3576_CRU_RESET_OFFSET(SRST_VICAP_I4CLK, 59, 5), > + > + /* SOFTRST_CON61 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 61, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP2_BIU, 61, 5), > + RK3576_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 61, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 61, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_VOP, 61, 8), > + RK3576_CRU_RESET_OFFSET(SRST_A_VOP, 61, 9), > + RK3576_CRU_RESET_OFFSET(SRST_D_VP0, 61, 13), > + > + /* SOFTRST_CON62 */ > + RK3576_CRU_RESET_OFFSET(SRST_D_VP1, 62, 0), > + RK3576_CRU_RESET_OFFSET(SRST_D_VP2, 62, 1), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOP2_BIU, 62, 2), > + RK3576_CRU_RESET_OFFSET(SRST_P_VOPGRF, 62, 3), > + > + /* SOFTRST_CON63 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 63, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 63, 7), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 63, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO0_GRF, 63, 10), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP0, 63, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP0, 63, 13), > + RK3576_CRU_RESET_OFFSET(SRST_HDCP0, 63, 14), > + > + /* SOFTRST_CON64 */ > + RK3576_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 64, 5), > + RK3576_CRU_RESET_OFFSET(SRST_DSIHOST0, 64, 6), > + RK3576_CRU_RESET_OFFSET(SRST_P_HDMITX0, 64, 7), > + RK3576_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 64, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_EDP0, 64, 13), > + RK3576_CRU_RESET_OFFSET(SRST_EDP0_24M, 64, 14), > + > + /* SOFTRST_CON65 */ > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI5_8CH, 65, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI5_8CH, 65, 5), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI6_8CH, 65, 8), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI6_8CH, 65, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX2, 65, 10), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX2, 65, 13), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_RX2, 65, 14), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_RX2, 65, 15), > + > + /* SOFTRST_CON66 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI8_8CH, 66, 0), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI8_8CH, 66, 2), > + > + /* SOFTRST_CON67 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VO1_BIU, 67, 5), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_BIU, 67, 6), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI7_8CH, 67, 9), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI7_8CH, 67, 10), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX3, 67, 11), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX4, 67, 12), > + RK3576_CRU_RESET_OFFSET(SRST_H_SPDIF_TX5, 67, 13), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX3, 67, 14), > + > + /* SOFTRST_CON68 */ > + RK3576_CRU_RESET_OFFSET(SRST_DP0, 68, 0), > + RK3576_CRU_RESET_OFFSET(SRST_P_VO1_GRF, 68, 2), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 68, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_HDCP1, 68, 4), > + RK3576_CRU_RESET_OFFSET(SRST_H_HDCP1, 68, 5), > + RK3576_CRU_RESET_OFFSET(SRST_HDCP1, 68, 6), > + RK3576_CRU_RESET_OFFSET(SRST_H_SAI9_8CH, 68, 9), > + RK3576_CRU_RESET_OFFSET(SRST_M_SAI9_8CH, 68, 11), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX4, 68, 12), > + RK3576_CRU_RESET_OFFSET(SRST_M_SPDIF_TX5, 68, 13), > + > + /* SOFTRST_CON69 */ > + RK3576_CRU_RESET_OFFSET(SRST_GPU, 69, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 69, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 69, 7), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 69, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 69, 13), > + RK3576_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 69, 14), > + RK3576_CRU_RESET_OFFSET(SRST_P_PVTPLL_GPU, 69, 15), > + > + /* SOFTRST_CON72 */ > + RK3576_CRU_RESET_OFFSET(SRST_A_CENTER_BIU, 72, 4), > + RK3576_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 72, 5), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 72, 6), > + RK3576_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 72, 7), > + RK3576_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 72, 8), > + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 72, 9), > + RK3576_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 72, 10), > + RK3576_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 72, 11), > + RK3576_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 72, 12), > + > + /* SOFTRST_CON75 */ > + RK3576_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 75, 1), > + > + /* SOFTRST_CON78 */ > + RK3576_CRU_RESET_OFFSET(SRST_DP0_PIXELCLK, 78, 1), > + RK3576_CRU_RESET_OFFSET(SRST_PHY_DP0_TX, 78, 2), > + RK3576_CRU_RESET_OFFSET(SRST_DP1_PIXELCLK, 78, 3), > + RK3576_CRU_RESET_OFFSET(SRST_DP2_PIXELCLK, 78, 4), > + > + /* SOFTRST_CON79 */ > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1_BIU, 79, 1), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1_BIU, 79, 2), > + RK3576_CRU_RESET_OFFSET(SRST_H_VEPU1, 79, 3), > + RK3576_CRU_RESET_OFFSET(SRST_A_VEPU1, 79, 4), > + RK3576_CRU_RESET_OFFSET(SRST_VEPU1_CORE, 79, 5), > + > + /* PPLL_SOFTRST_CON00 */ > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PHPPHY_CRU, 0, 1), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 3), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0, 0, 5), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY0_GRF, 0, 6), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1, 0, 7), > + RK3576_PHPCRU_RESET_OFFSET(SRST_P_PCIE2_COMBOPHY1_GRF, 0, 8), > + > + /* PPLL_SOFTRST_CON01 */ > + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE0_PIPE_PHY, 1, 5), > + RK3576_PHPCRU_RESET_OFFSET(SRST_PCIE1_PIPE_PHY, 1, 8), > + > + /* SECURENS_SOFTRST_CON00 */ > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_CRYPTO_NS, 0, 3), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_H_TRNG_NS, 0, 4), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_P_OTPC_NS, 0, 8), > + RK3576_SECURENSCRU_RESET_OFFSET(SRST_OTPC_NS, 0, 9), > + > + /* PMU1_SOFTRST_CON00 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_GRF, 0, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_HDPTX_APB, 0, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY, 0, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_DCPHY_GRF, 0, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT0_APB2ASB, 0, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_BOT1_APB2ASB, 0, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USB2DEBUG, 0, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY_GRF, 0, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CSIPHY, 0, 8), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_0, 0, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBPHY_GRF_1, 0, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDP_GRF, 0, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_USBDPPHY, 0, 12), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_INIT, 0, 15), > + > + /* PMU1_SOFTRST_CON01 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_CMN, 1, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_LANE, 1, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY_PCS, 1, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY, 1, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY, 1, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_SCAN_CSIPHY, 1, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO6_IOC, 1, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_0, 1, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_1, 1, 8), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_INIT, 1, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_CMN, 1, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDPTX_LANE, 1, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_HDMITXHPD, 1, 13), > + > + /* PMU1_SOFTRST_CON02 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_MPHY_INIT, 2, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_MPHY_GRF, 2, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_VCCIO7_IOC, 2, 3), > + > + /* PMU1_SOFTRST_CON03 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 3, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_NIU, 3, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 3, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_CORE, 3, 12), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU_CM0_JTAG, 3, 13), > + > + /* PMU1_SOFTRST_CON04 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 4, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 4, 3), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 4, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 4, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 4, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMUTIMER, 4, 7), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER0, 4, 9), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMUTIMER1, 4, 10), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 4, 11), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 4, 12), > + > + /* PMU1_SOFTRST_CON05 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 5, 1), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_I2C0, 5, 2), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_S_UART1, 5, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_UART1, 5, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_PDM0, 5, 13), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 5, 15), > + > + /* PMU1_SOFTRST_CON06 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_M_PDM0, 6, 0), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 6, 1), > + > + /* PMU1_SOFTRST_CON07 */ > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 7, 4), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 7, 5), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 7, 6), > + RK3576_PMU1CRU_RESET_OFFSET(SRST_DB_GPIO0, 7, 7), > +}; > + > +void rk3576_rst_init(struct device_node *np, void __iomem *reg_base) > +{ > + rockchip_register_softrst_lut(np, > + rk3576_register_offset, > + ARRAY_SIZE(rk3576_register_offset), > + reg_base + RK3576_SOFTRST_CON(0), > + ROCKCHIP_SOFTRST_HIWORD_MASK); > +} > + ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2024-08-26 14:00 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-08-22 19:49 [PATCH v6 0/3] Add CRU support for rk3576 SoC Detlev Casanova 2024-08-22 19:49 ` [PATCH v6 1/3] dt-bindings: clock, reset: Add support for rk3576 Detlev Casanova 2024-08-26 11:04 ` Andy Yan 2024-08-26 14:00 ` [PATCH " Rob Herring (Arm) 2024-08-22 19:49 ` [PATCH v6 2/3] clk: rockchip: Add new pll type pll_rk3588_ddr Detlev Casanova 2024-08-23 5:15 ` Dragan Simic 2024-08-22 19:49 ` [PATCH v6 3/3] clk: rockchip: Add clock controller for the RK3576 Detlev Casanova 2024-08-23 5:16 ` Dragan Simic
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®